1. A display system comprising:
means for inputting source image data renderable upon a first display of a first subpixel format having a first resolution;
a second display of a second subpixel format, said second subpixel format comprising fewer subpixels than said first subpixel format; and
means for generating intensity coefficients for each subpixel of said second display, said means for generating intensity coefficients further comprising a two-dimensional area sample mapping of said source image data into a target image data, said target image data renderable upon said second display at said first resolution.
2. The display system of claim 1 wherein said two-dimensional area sample mapping further comprises:
means for dividing the source image data into a plurality of sample areas of said first display;
for each color plane, means for tiling said plurality of sample areas with a plurality of resample areas, each said resample area having an area larger than each said sample area;
means for determining filter kernals, said filter kernals comprising fractional coefficients based upon the amount of overlapping areas of said resample area into said sample areas.
3. The display system of claim 2, wherein each said resample area is one of the group, said group comprising squares, rectangles, triangles, hexagons, octagons, diamonds, staggered squares, staggered rectangles, staggered triangles, Penrose tiles, rhombuses, distorted rhombuses, and staggered diamonds.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a cylindrical type capacitor structure formed in a cell region over a semiconductor substrate, the structure including a cylindrical type lower electrode, a dielectric and an upper electrode;
a storage node oxide formed in a peripheral region over the semiconductor substrate;
a conductive layer coating a guard ring hole, the guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate;
a capping oxide partially filling in a part of the conductive layer; and
a gapfill film filling in a remaining part of the conductive layer.
2. The device of claim 1, wherein the gapfill film has an etch selectivity against removal by a wet dip-out process as opposed to the storage node oxide.
3. The device of claim 1, wherein the capping oxide comprises at least one of a low-temperature silicon oxide, PSG-based (phosphorsilicate glass) film or USG-based (undoped silicate glass) film.
4. The device of claim 3, wherein the low-temperature silicon oxide includes SiO2 film obtained by adding O3 to TDMAS (tris(dimethylamino)silane), ALD SiO2 film obtained by adding pyridine to HCD.
5. The device of claim 3, wherein the low-temperature silicon oxide includes SiO2 film obtained by adding O3 to TDMAS (tris(dimethylamino)silane), ALD SiO2 film obtained by adding pyridine to HCD.
6. The device of claim 1, wherein the gapfill film comprises a metallic film selected from the group consisting of TiN, TaN, WN, Pt, Ru, TiSiN, TiSiCN, TiCN and TiAlN, or a silicon-based film selected from the group consisting of Si3N4, SiON, SiBN, Si and SiGe.
7. The device of claim 1, wherein the lower electrode and the gapfill film are made of the same material.
8. The device of claim 1, wherein the storage node oxide includes single layer film made from PSG (phosphorsilicate glass), BSG (boro-silicate glass), BPSG (borophosphorsilicate glass), USG (undoped silicate glass), TEOS (tetraethyl orthosilicate) or a multilayer film thereof.
9. The device of claim 1, wherein the lower electrode includes any of TiN, TaN, WN, Pt, Ru or AlN, or a laminate thereof, or a film made of the aforementioned materials coupled with Si, C, Al and Ge.
10. The device of claim 1, wherein the dielectric includes any of Al2O3, ZrO2, HfO2, Ta2O5, TiO2, STO, BST, PZT, or a multilayer film thereof.
11. The device of claim 1, wherein the upper electrode includes any of TiN, TaN, WWN, WN, Pt, Ru and AlN, or a laminate thereof.
12. The device of claim 1, wherein the gapfill film has an etch selectivity against removal by a wet dip-out process as opposed to the storage node oxide.
13. The device of claim 1, wherein the capping oxide comprises at least one of a low-temperature silicon oxide, PSG-based (phosphorsilicate glass) film or USG-based (undoped silicate glass) film.
14. The device of claim 1, wherein the gapfill film comprises a metallic film selected from the group consisting of TiN, TaN, WN, Pt, Ru, TiSiN, TiSiCN, TiCN and TiAlN, or a silicon-based film selected from the group consisting of Si3N4, SiON, SiBN, Si and SiGe.
15. The device of claim 1, wherein the lower electrode and the gapfill film are made of the same material.
16. The device of claim 1, wherein the storage node oxide includes single layer film made from PSG (phosphorsilicate glass), BSG (boro-silicate glass), BPSG (borophosphorsilicate glass), USG (undoped silicate glass), TEOS (tetraethyl orthosilicate) or a multilayer film thereof.
17. The device of claim 1, wherein the lower electrode includes any of TiN, TaN, WN, Pt, Ru or AlN, or a laminate thereof, or a film made of the aforementioned materials coupled with Si, C, Al and Ge.
18. The device of claim 1, wherein the dielectric includes any of Al2O3, ZrO2, HfO2, Ta2O5, TiO2, STO, BST, PZT, or a multilayer film thereof.
19. The device of claim 1, wherein the upper electrode includes any of TiN, TaN, WWN, WN, Pt, Ru and AlN, or a laminate thereof.
20. A semiconductor device, comprising:
a capacitor structure formed in a cell region over a semiconductor substrate, the structure including a lower electrode, a dielectric and an upper electrode;
a storage node oxide formed in a peripheral region over the semiconductor substrate;
a conductive layer coating a guard ring hole, the guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate;
a capping oxide partially filling in a part of the conductive layer; and
a gapfill film filling in a remaining part of the conductive layer.