1: A driving power supply circuit for controlling a driving voltage to have the voltage between a lower reference voltage and a upper reference voltage and for outputting said driving voltage from an output comprising;
a p-channel MOS transistor being connected between a power supply voltage and said output node and being configured to become on-state when a first signal has a low logic level (hereinafter referred to as level \u201cL\u201d) and become off-state when said first signal has a high level (hereinafter referred to as level \u201cH\u201d);
a n-channel MOS transistor being connected between said output node and a ground voltage and being configured to become off-state when a second signal has level \u201cL\u201d and become on-state when said second signal has level \u201cH\u201d;
a first comparing circuit being configured to compare said driving voltage to said reference voltage when said second signal has level \u201cL\u201d, being configured to set said first signal to level \u201cH\u201d and output said first signal when said driving voltage is higher than said reference voltage, and being configured to set said first signal to level \u201cL\u201d and output said first signal when said driving voltage is lower than said reference voltage, and being configured to halt the operation thereof, set said first signal to level \u201cH\u201d, and output said first signal when said second signal has level \u201cL\u201d;
a second comparing circuit being configured to compare said driving voltage to said reference voltage when said second signal has level \u201cH\u201d, being configured to set said second signal to level \u201cH\u201d and output said second signal when said driving voltage is higher than said reference voltage, being configured to set said second signal to level \u201cL\u201d and output said second signal when said driving voltage is lower than said reference voltage, and being configured to halt the operation thereof, set said second signal to level \u201cL\u201d, and output said second signal when said first signal has level \u201cL\u201d.
2. A driving power supply circuit for controlling a driving voltage to have the voltage between a lower reference voltage and a upper reference voltage and for outputting said driving voltage from an output comprising;
a p-channel MOS transistor being connected between a power supply voltage and said output node and being configured to become on-state when a first signal has level \u201cL\u201d and become off-state when said first signal has level \u201cH\u201d;
a n-channel MOS transistor being connected between said output node and a ground voltage and being configured to become off-state when a second signal has level \u201cL\u201d and become on-state when said second signal has level \u201cH\u201d;
a logic circuit being configured to output a first control signal when said first signal and said second signal have level \u201cL\u201d, being configured to output a second control signal when said first signal and said second signal have level \u201cH\u201d, and being configured to output a third control signal when said first signal has level \u201cH\u201d and said second signal have level \u201cL\u201d;
a first comparing circuit being configured to compare said driving voltage to said reference voltage in a high-speed-operation mode when said first control signal is provided thereto, being configured to compare said driving voltage to said reference voltage in a low-power-consumption mode when said third control signal is provided thereto, being configured to set said first signal to level \u201cH\u201d and output said first signal when said driving voltage is higher than said reference voltage, and being configured to set said first signal to level \u201cL\u201d and output said first signal when said driving voltage is lower than said reference voltage;
a second comparing circuit being configured to compare said driving voltage to said reference voltage in a high-speed-operation mode when said second control signal is provided thereto, being configured to compare said driving voltage to said reference voltage in a low-power-consumption mode when said third control signal is provided thereto, being configured to set said second signal to level \u201cH\u201d and output said second signal when said driving voltage is higher than said reference voltage, being configured to set said second signal to level \u201cL\u201d and output said second signal when said driving voltage is lower than said reference voltage.
3. The driving voltage circuit according to claim 2, being configured to output said first, said second, and said third control signal in the case where a changing signal indicating that a load side circuit supplying said driving voltage is changed is given thereto when said first signal has level \u201cH\u201d and said second signal has level \u201cL\u201d.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A transceiver, comprising:
a transmitter portion including a digital-to-analog converter (DAC);
a receiver portion configured to receive RF signals in a receive frequency band; and
a variable rate clock generator operable to control said DAC,
wherein the rate of a variable rate clock provided by the variable rate clock generator is adjustable so that an upconverted version of a DAC image created by said DAC is shifted in frequency away from frequencies within said receive frequency band.
2. The transceiver of claim 1, further comprising a data rate converter configured to receive digital data and provide rate converted digital data to said DAC.
3. The transceiver of claim 2 wherein the data rate converter provides said rate converted data to said DAC according to the variable rate clock provided by the variable rate clock generator.
4. The transceiver of claim 1 wherein the transmitter portion further includes a digital filter that functions as a notch filter, said digital filter configured so that its notch frequency falls within the receive frequency band.
5. The transceiver of claim 4 wherein the digital filter is controlled by the variable rate clock provided by the variable rate clock generator.
6. The transceiver of claim 4, further comprising a data rate converter configured to receive digital data and provide rate converted digital data to said DAC.
7. The transceiver of claim 6 wherein the data rate converter provides said rate converted data according to the variable rate clock provided by the variable rate clock generator.
8. The transceiver of claim 6 wherein the functionality of the data rate converter is merged with the functionality of the digital filter.
9. A method of processing signals in a transceiver, comprising:
receiving a digital baseband signal from a digital source;
converting the digital baseband signal to an analog baseband signal according to an adjustable oversampling clock; and
upconverting the analog baseband signal to a radio frequency (RF) signal,
wherein converting the digital baseband signal to an analog baseband signal includes adjusting the rate of the adjustable oversampling clock so that an image created by the conversion process does not fall within a receive frequency band when the image is upconverted to RF by the upconversion process.
10. The method of claim 9, further comprising filtering the digital baseband signal using a digital low-pass filter that functions as a notch filter.
11. The method of claim 10 wherein a notch frequency of said the digital low-pass filter is configured so that it falls within the receive frequency band.
12. The method of claim 11 wherein the notch frequency of the digital low-pass filter is controlled by the adjustable oversampling clock.
13. A transceiver capable of transmitting and receiving in different transmit and frequency bands, comprising:
a polar modulation transmitter having a magnitude path and a phase path, at least one of said magnitude and phase paths having a digital-to-analog converter (DAC) configured to receive digital baseband signals from a digital source;
a receiver that can be configured to receive radio frequency (RF) signals in any one of several possible receive frequency bands; and
an oversampling clock generator operable to provide an oversampling clock to a clock input of said DAC, wherein the oversampling clock provided by the oversampling clock generator is adjustable so that a DAC image created by the DAC and upconverted to RF is shifted away from the receive frequency band in which the receiver is configured to receive.
14. The transceiver of claim 13 wherein at least one of said magnitude and phase paths of said transmitter includes a digital filter that operates as a notch filter.
15. The transceiver of claim 14 wherein the digital filter is configured so that its notch frequency falls within the frequency band in which the receiver is configured to receive.
16. The transceiver of claim 14 wherein the digital filter is controlled by the variable rate oversampling clock provided by the oversampling clock generator.
17. A mobile communication device, comprising:
baseband circuitry operable to generate digital symbols;
a transmitter having a digital-to-analog converter (DAC) that is operable to convert the digital symbols to analog signals;
a receiver configured to receive RF signals in one or more receive frequency bands; and
means for frequency shifting an upconverted version of a DAC image created by the DAC to a frequency region that does not substantially overlap with a receive frequency band in which the receiver is configured to receive.
18. The mobile communication device of claim 17 wherein said means for shifting a DAC image is configured to frequency shift the DAC image by an amount that depends on which one of said one or more receive frequency bands the receiver is configured to receive.
19. The mobile communication device of claim 18 wherein the transmitter further comprises a digital filter configured to filter the digital symbols, said digital filter having an adjustable notch frequency.
20. The mobile communication device of claim 19 wherein the digital filter is controlled by a sampling clock provided by the means for frequency shifting a DAC image.
21. A transceiver, comprising:
a transmitter portion including a digital-to-analog converter (DAC);
a receiver portion configured to receive RF signals in a receive frequency band; and
a variable rate clock generator operable to control said DAC,
wherein the rate of a variable rate clock provided by the variable rate clock generator is determined based on an operating band of a standard the transceiver is currently configured to operate in.