1. A hollow golf club head comprising:
a face for hitting a ball having a periphery and a face centroid, and
a face peripheral portion extending rearward of the head from the periphery of the face and provided with only two reduced-rigidity portions,
said each of the reduced-rigidity portions provided on the side of the hollow of the club head and consisting of a concave portion extending along the periphery of the face, said each of the reduced-rigidity portions having a depth in a range of from 0.2 to 1.0 mm and a width in a range of from 0.2 to 3.0 mm in a cross section perpendicular to a longitudinal direction of the concave portion, wherein
in a standard state in which the head is placed on a horizontal plane so that a centerline of a shaft axis of the head is inclined at its lie angle within a vertical plane and the face is held at its loft angle,
the reduced-rigidity portions consist of one toe-side reduced-rigidity portion provided on the toe side of the face centroid and one heel-side reduced-rigidity portion provided on the heel side of the face centroid, and
when the head in the standard state is viewed from a direction of a normal of the face centroid,
said toe-side reduced-rigidity portion has a center point P1 of its length located higher at the toe side of the face centroid, wherein an angle \u03b8t of a first straight line connecting the face centroid with the center point P1 of the toe-side reduced-rigidity portion with respect to the horizontal plane is in a range of from 30 to 45 degrees, and
the heel-side reduced-rigidity portion has a center point P2 of its length located lower and the heel side of the face centroid, wherein an angle \u03b8h of a second straight line connecting the face centroid with the center point P2 of the heel-side reduced-rigidity portion with respect to the horizontal plane is in a range of from 30 to 50 degree.
2. The golf club head according to claim 1, wherein the head comprises:
a cup-shaped face member having the face and a flange portion which extends rearward of the head from the periphery of the face to constitute the face peripheral portion, and
a head main body fixed to a rear side of the face member.
3. The golf club head according to claim 1, wherein said each reduced-rigidity portion has a longitudinal length in a range of from 5 to 60 mm.
4. The golf club head according to claim 1, wherein said reduced-rigidity portions has a smooth curved shape in a cross section perpendicular to the longitudinal of the concave portion.
5. The golf club head according to claim 1, wherein said reduced-rigidity portions are arranged on a corner formed between the face peripheral portion and the face, in a cross section perpendicular to the longitudinal direction of the concave portion.
6. The golf club head according to claim 1, wherein the face peripheral portion is an area within 10 mm from the periphery of the face to the rearward of the head.
7. The golf club head according to claim 1, wherein the angle \u03b8t is smaller than the angle \u03b8h.
8. The golf club head according to claim 1, wherein said toe-side reduced-rigidity portion and said heel-side reduced-rigidity portion have the same longitudinal length.
9. The golf club head according to claim 1, wherein the face peripheral portion has a flat exterior surface so that each of said toe-side reduced-rigidity portion and said heel-side reduced-rigidity portion has a small thickness.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:
a current mirror circuit that provides an output signal in the second power domain, the current mirror comprising:
first and second p-type transistors coupled to the second supply voltage;
first and second zero threshold n-type transistors coupled to respective ones of the first and second p-type transistors; and
first and second n-type transistors coupled to respective ones of the first and second p-type transistors through respective ones of the first and second zero threshold transistors, the first and second n-type transistors having a threshold voltage based on the first supply voltage; and
a switching control circuit utilizing the first supply voltage that controls the first zero threshold transistor responsive to the input signal.
2. The level shifter circuit of claim 1, wherein the switching control circuit comprises a delay circuit configured to delay the input signal to provide a delayed input signal to control the first zero threshold transistor.
3. The level shifter of claim 2, wherein the delay circuit has a delay corresponding to a delay between a transition in the input signal and a corresponding transition in the output signal.
4. The level shifter of claim 1, wherein a voltage between the source and drain of the first and second n-type transistors is limited to the first supply voltage minus a threshold voltage of the corresponding first and second zero threshold transistors.
5. A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:
a current mirror circuit that provides an output signal in the second power domain, the current mirror comprising:
first and second p-type transistors coupled to the second supply voltage;
first and second zero threshold n-type transistors coupled to respective ones of the first and second p-type transistors; and
first and second n-type transistors coupled to respective ones of the first and second p-type transistors through respective ones of the first and second zero threshold transistors, the first and second n-type transistors having a threshold voltage based on the first supply voltage;
a switching control circuit utilizing the first supply voltage that controls the first zero threshold transistor responsive to the input signal, wherein the switching control circuit comprises a delay circuit configured to delay the input signal to provide a delayed input signal to control the first zero threshold transistor;
a first inverter utilizing the first supply voltage and configured to receive the input signal and provide an inverted input signal to the first n-type transistor;
a second inverter utilizing the first supply voltage and configured to receive the inverted input signal and provide a buffered input signal to the second n-type transistor; and
a third inverter utilizing the second supply voltage and to provide the output signal.
6. The level shifter of claim 5, wherein the delay circuit comprises at least two series inverters utilizing the first supply voltage.
7. The level shifter of claim 5, wherein the delay circuit comprises:
a fourth inverter utilizing the first supply voltage and configured to receive the input signal and provide a second inverted input signal;
a NOR gate utilizing the first supply voltage and configured to receive the input signal and the second inverted input signal and provide a logical NOR of the input signal and the second inverted input signal to the first zero threshold transistor.
8. The level shifter of claim 5, further comprising a third p-type transistor having a gate coupled to the output of the third inverter and that couples the second supply voltage to the input of the third inverter.
9. The level shifter of claim 5, further comprising a fourth p-type transistor having a gate coupled to the input of the third inverter and couples the second supply voltage to the gates of the first and the second p-type transistors.
10. The level shifter of claim 5, wherein a gate of the second zero threshold transistor is coupled to the output of the second inverter.
11. The level shifter of claim 5, wherein a gate of the second zero threshold transistor is coupled to the first supply voltage.
12. The level shifter of claim 5, wherein the delay circuit has a delay corresponding to a delay between a transition in an output of the first inverter and a corresponding transition in the output signal.
13. A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:
first and second cross-coupled p-type transistors coupled to the second supply voltage;
first and second zero threshold n-type transistors serially coupled to the first p-type transistor and responsive to an inverted input signal; and
third and fourth zero threshold n-type transistors serially coupled to the second p-type transistor and responsive to an buffered input signal.
14. The level shifter of claim 13, wherein a gate oxide of the first and second cross-coupled p-type transistors and the first, second, third and fourth zero threshold transistors is substantially the same.
15. The level shifter of claim 13, further comprising:
a first inverter utilizing the first supply voltage and configured to receive the input signal and provide the inverted input signal to the first and second zero threshold transistors;
a second inverter utilizing the first supply voltage and configured to receive the inverted input signal and provide the buffered input signal to the third and fourth zero threshold transistors; and
a third inverter utilizing the second supply voltage and to provide the output signal.
16. A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:
first and second p-type transistors coupled to the second supply voltage having connected gate electrodes;
first and second zero threshold n-type transistors serially coupled to the first p-type transistor and responsive to an inverted input signal;
third and fourth zero threshold n-type transistors serially coupled to the second p-type transistor and responsive to an buffered input signal; and
a switching control circuit utilizing the first supply voltage that controls the first zero threshold transistor responsive to the input signal.
17. The level shifter of claim 16, wherein a gate oxide of the first and second p-type transistors and the first, second, third and fourth zero threshold transistors is substantially the same.
18. The level shifter of claim 16, further comprising:
a first inverter utilizing the first supply voltage and configured to receive the input signal and provide the inverted input signal to the first and second zero threshold transistors;
a second inverter utilizing the first supply voltage and configured to receive the inverted input signal and provide the buffered input signal to the third and fourth zero threshold transistors; and
a third inverter utilizing the second supply voltage and to provide the output signal.
19. The level shifter of claim 18, wherein the switching control circuit comprises at least two series inverters utilizing the first supply voltage.
20. The level shifter of claim 18, wherein the switching control circuit comprises:
a fourth inverter utilizing the first supply voltage and configured to receive the input signal and provide a second inverted input signal;
a NOR gate utilizing the first supply voltage and configured to receive the input signal and the second inverted input signal and provide a logical NOR of the input signal and the second inverted input signal to the first zero threshold transistor.
21. The level shifter of claim 18, further comprising a third p-type transistor having a gate coupled to the output of the third inverter and that couples the second supply voltage to the input of the third inverter.
22. The level shifter of claim 18, further comprising a fourth p-type transistor having a gate coupled to the input of the third inverter and couples the second supply voltage to the gates of the first and the second p-type transistors.
23. The level shifter of claim 16, wherein the switching control circuit comprises a delay circuit that has a delay corresponding to a delay between a transition in the input signal and a corresponding transition in the output signal.