1. A communication device comprising:
a signal strength check unit configured to check the signal strength of a radio signal using a broad radio frequency range; and
a communication target detection unit configured to detect a communication target in descending order of the signal strength of the radio signal, which is checked by the signal strength check unit, for each frequency band that is included in the broad radio frequency range.
2. The communication device according to claim 1, wherein
the signal strength check unit is configured to check the signal strength of the radio signal using the broad radio frequency range, and to check the signal strength of the radio signal using a radio frequency range that is narrower than the broad radio frequency range, in the broad radio frequency range in descending order of checked signal strength of the radio signal, and
the communication target detection unit is configured to detect the communication target for each frequency that is included in the narrower radio frequency range in descending order of the signal strength of the radio signal, which is checked by the signal strength check unit.
3. The communication device according to claim 1, wherein
the communication target detection unit is configured to detect the communication target from a frequency band that is a center of the broad radio frequency range, out of frequency bands that are included in the broad radio frequency range.
4. The communication device according to claim 1, wherein
the communication device is constituted by a module.
5. The communication device according to claim 1, wherein
the communication device is constituted by an integrated device.
6. The communication device according to claim 1, further comprising:
a display control unit configured to control display of the communication target that is detected by the communication target detection unit each time the communication target detection unit terminates the detection of the communication target for each of the frequency bands.
7. The communication device according to claim 1, wherein
the communication target is an access point.
8. A communication method comprising;
checking the signal strength of a radio signal using a broad radio frequency range by a communication device; and
detecting a communication target in descending order of checked signal strength of the radio signal, for each frequency band that is included in the broad radio frequency range.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of operating an integrated circuit, comprising:
at a transmitter circuit, transmitting signals as a timed sequence of binary valued bits, the binary valued bits including a first binary value and a second binary value, the transmitting of the first binary value consuming more power relative to transmitting the second binary value;
the transmitting of signals to indicate the time sequence of binary valued bits comprising:
in response to a first at least one bit and a second at least one bit that all have the first binary value and are in succession in the time sequence of binary valued bits, outputting a signal to indicate the second at least one bit that consumes less power than a signal used to signal the first at least one bit.
2. The method of claim 1, wherein the transmitting of signals to indicate the time sequence of binary valued bits further comprises:
in response to the first at least one bit, the second at least one bit, and a third at least one bit that all have the first binary value and are in succession in the time sequence of binary valued bits, outputting a signal to indicate the third at least one bit that consumes less power than a signal used to signal the first at least one bit.
3. The method of claim 1, wherein the transmitting of signals to indicate the time sequence of binary valued bits further comprises:
in response to the first at least one bit, the second at least one bit, and a third at least one bit that all have the first binary value and are in succession, outputting a signal to indicate the third at least one bit that consumes less power than a signal used to signal the second at least one bit.
4. The method of claim 1, wherein the first at least one bit is in succession in the time sequence of binary values immediately after at least one bit having the second binary value.
5. The method of claim 1, wherein a variable strength driver is controlled to output the signal used to signal the first at least one bit and the signal to indicate the second at least one bit.
6. The method of claim 5, wherein the variable strength driver outputs the signal used to signal the first at least one bit using a first signaling level and first drive strength that remains substantially constant during an outputting of the first at least one bit.
7. The method of claim 6, wherein the variable strength driver outputs the signal used to signal the second at least one bit using a plurality of signaling levels and a plurality of drive strengths that adjust during an outputting of the second at least one bit.
8. An integrated circuit, comprising:
an output driver to transmit signals to indicate a time sequence of binary valued bits comprising a first binary value and a second binary value, the first binary value consuming more power to transmit than the second binary value; and,
driver control circuitry to, in response to a first at least one bit and a second at least one bit that all have the first binary value and are in succession, control the output driver to transmit a signal to indicate the second at least one bit that consumes less power than a signal used to transmit the first at least one bit.
9. The integrated circuit of claim 8, wherein the driver control circuitry is to, in response to the first at least one bit, the second at least one bit, and a third at least one bit that all have the first binary value and are in succession, control the output driver to transmit a signal to indicate the third at least one bit that consumes less power than a signal used to transmit the first at least one bit.
10. The integrated circuit of claim 8, wherein the driver control circuitry is to, in response to the first at least one bit, the second at least one bit, and a third at least one bit that all have the first binary value and are in succession, control the output driver to transmit a signal to indicate the third at least one bit that consumes less power than a signal used to transmit the second at least one bit.
11. The integrated circuit of claim 8, wherein the first at least one bit is to be in succession in the time sequence of binary values immediately after at least one bit having the second binary value.
12. The method of claim 8, wherein the driver control circuitry controls a variable strength driver to transmit the signal to indicate the second at least one bit that consumes less power than the signal used to transmit the first at least one bit.
13. The method of claim 12, wherein the variable strength driver outputs a signal used to transmit the first at least one bit using a first signaling level and first drive strength that remains substantially constant during an outputting of the first at least one bit.
14. The method of claim 13, wherein the variable strength driver outputs a signal used to transmit the second at least one bit using a plurality of signaling levels and a plurality of drive strengths that adjust during an outputting of the second at least one bit.
15. A method of operating an integrated circuit, comprising:
outputting a time series of signals to indicate a time series of binary valued bits, a first binary value consuming more power to signal than a second binary value;
wherein a first bit having the first binary value is signaled using a first signaling power level, the first bit occurring in the time series of binary valued bits immediately after a bit having the second binary value; and,
wherein a second bit having the first binary value is signaled using a second signaling power level, the second bit occurring in the time series of binary valued bits immediately after the first bit, the second signaling power level consuming less power than the first signaling power level.
16. The method of claim 15, wherein a third bit having the first binary value is signaled using the second signaling power level, the third bit occurring in the time series of binary valued bits immediately after the second bit.
17. The method of claim 15, wherein a third bit having the first binary value is signaled using a third signaling power level, the third bit occurring in the time series of binary valued bits immediately after the second bit, the third signaling power level consuming less power than the second signaling power level.
18. The method of claim 15, further comprising:
controlling a variable strength driver to signal using the first signaling power level and to signal using the second signaling power level.
19. The method of claim 18, wherein the variable strength driver signals the second binary value using a first signaling level and first drive strength that remains substantially constant during a signaling of the second binary value.
20. The method of claim 19, wherein the variable strength driver signals the first binary value using a plurality of signaling levels and a plurality of drive strengths that adjust during an outputting of the first bit and the second bit.