1. A decoder circuit of a semiconductor storage device, comprising:
a word line selection circuit that includes voltage application MOS transistors corresponding to each of a plurality of word lines that apply a normal voltage to the word lines corresponding to memory cells selected among a plurality of memory cells positioned at a portion where the plurality of word lines intersect a plurality of bit lines in a predetermined normal operation, and that applies a high voltage higher than the normal voltage in a predetermined high voltage operation; and
a level shift circuit that outputs, to the voltage application MOS transistor, at least one of the normal voltage or a ground voltage lower than the normal voltage according to a selection state of the word line in the normal operation, and that outputs, to the voltage application MOS transistor, at least one of the normal voltage or the high voltage according to a selection state of the word line in the high voltage operation.
2. The decoder circuit of a semiconductor storage device of claim 1,
wherein the voltage application MOS transistors of the word line selection circuit includes PMOS transistors,
wherein the word line selection circuit includes a control PMOS transistor that controls output of a voltage to the voltage application MOS transistor, including a source to which the normal voltage is input when the word line selection circuit performs the normal operation, and to which the high voltage is input when the word line selection circuit performs the high voltage operation, and a drain connected to a source of the voltage application MOS transistor, and
wherein the level shift circuit includes,
a PMOS transistor including a source to which the normal voltage is input in the normal operation, and to which the high voltage is input in the high voltage operation, and a gate to which the normal voltage is input when the word line is selected in the normal operation, to which the ground voltage is input when the word line is not selected in the normal operation, and to which the normal voltage is constantly input in the high voltage operation,
a first DMOS transistor, connected to the PMOS transistor in series, including a gate and a source connected to a gate of the control PMOS transistor,
a second DMOS transistor, connected to the first DMOS transistor in series, including a gate to which a selection signal, that becomes active when the word line is selected, is input,
a first NMOS transistor, connected to the second DMOS transistor in series, including a gate to which the selection signal is input, and
a second NMOS transistor, connected to the first NMOS transistor in parallel, including a gate to which the ground voltage is input in the normal operation, and to which the high voltage is input in the high voltage operation, and a source to which the ground voltage is input in the normal operation, and to which the normal voltage is input in the high voltage operation.
3. The decoder circuit of a semiconductor storage device of claim 1,
wherein the voltage application MOS transistors of the word line selection circuit includes PMOS transistors including a source to which the normal voltage is input in the normal operation and to which the high voltage is input in the high voltage operation, and
wherein the level shift circuit includes,
a PMOS transistor including a source to which the normal voltage is input in the normal operation, and to which the high voltage is input in the high voltage operation, and a gate to which the normal voltage is input when the word line is selected in the normal operation, to which the ground voltage is input when the word line is not selected in the normal operation, and to which the-normal voltage is constantly input in the high voltage operation,
a first DMOS transistor, connected to the PMOS transistor in series, including a gate and a source connected to a gate of the voltage application MOS transistor,
a second DMOS transistor, connected to the first DMOS transistor in series, including a gate to which a selection signal, that becomes active when the word line is selected, is input,
a first NMOS transistor, connected to the second DMOS transistor in series, including a gate to which the selection signal is input, and
a second NMOS transistor, connected to the first NMOS transistor in parallel, including a gate to which the ground voltage is input in the normal operation, and to which the high voltage is input in the high voltage operation, and a source to which the ground voltage is input in the normal operation, and to which the normal voltage is input in the high voltage operation.
4. The decoder circuit of a semiconductor storage device of claim 2, further comprising a third DMOS transistor connected to the first DMOS transistor in parallel.
5. The decoder circuit of a semiconductor storage device of claim 3, further comprising a third DMOS transistor connected to the first DMOS transistor in parallel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A coding method, comprising:
multiplexing a plurality of kinds of variable-length codes generated by compression coding of an input image signal to generate a multiplexed code string;
assembling an output code string by using the multiplexed code string as an input; and
inserting a synchronization code to a selected one of a plurality of synchronization code inserting positions periodically predetermined in the output code string, and inserting a stuffing code, a first bit of the stuffing code being a first value, and when there is a subsequent bit following the first bit of the stuffing code, the subsequent bit of the stuffing code is a second value.
2. A coding apparatus, comprising:
a multiplexer configured to multiplex a plurality of kinds of variable-length codes generated by variable-length coding of an input image signal to generate a multiplexed code string; and
a coding assembler configured to assemble an output code string by using the multiplexed code string as an input, the coding assembler inserting a synchronization code to a selected one of a plurality of synchronization code inserting positions periodically predetermined in the output code string, and inserting a stuffing code, a first bit of the stuffing code being a first value, and when there is a subsequent bit following the first bit of the stuffing code, the subsequent bit of the stuffing code is a second value.
3. The coding apparatus according to claim 2, wherein the multiplexer multiplexes the variable-length codes by units that are each a frame of the image signal.
4. The coding apparatus according to claim 2, wherein the multiplexer multiplexes the variable-length codes by units that are each a partial area in a frame of the image signal.
5. The coding apparatus according to claim 2, wherein
the multiplexer multiplexes the variable-length codes by units that are each a frame of the image signal; and
the coding assembler inserts the synchronization code to the synchronization code inserting position located just before or just after an end portion of each multiplexed portion in the multiplexed code string, the multiplexed portion being multiplexed in units of the frame.
6. The coding apparatus according to claim 2, wherein
the multiplexer multiplexes the variable-length code by units that are each a partial area in a frame of the image signal; and
the coding assembler inserts the synchronization code to the synchronization code inserting position located just before or just after an end portion of each multiplexed portion in the multiplexed code string, the multiplexed portion being multiplexed in units of the partial area.
7. The coding apparatus according to claim 2, further comprising a code string converter which converts a code string except for the synchronization code located to the synchronization code inserting position in the output code string to set a Hamming distance from the synchronization code to be equal to or more than a predetermined value.
8. The coding apparatus according to claim 2,
wherein the stuffing code has a value in which a Hamming distance between the synchronization code and a portion thereof is equal to or more than a predetermined value.
9. The coding apparatus according to claim 8,
wherein the code string assembler arranges the stuffing code just before the synchronization code.