1. A display panel comprising a pixel substrate on which a plurality of display pixels are formed in a matrix form and a sealing substrate having a peripheral portion joined to a peripheral portion of the pixel substrate for sealing a space above the pixel substrate, wherein
the pixel substrate and the sealing substrate are joined and sealed at the peripheral portion by a metal joint solder layer which is formed through patterning, and
the surfaces of the pixel substrate, the sealing substrate, or the pixel substrate and the sealing substrate have projections and depressions in a formation region of the joint solder layer.
2. A display panel according to claim 1, wherein the solder layer is formed directly on the pixel substrate, the sealing substrate, or the pixel substrate and the sealing substrate.
3. A display panel according to claim 1, further including
a metal layer formed on the pixel substrate, the sealing substrate, or the pixel substrate and the sealing substrate, and having a high adhesion property with the solder layer,
wherein the solder layer is formed on the metal layer.
4. A display panel comprising a pixel substrate on which a plurality of display pixels are formed in a matrix form and a sealing substrate having a peripheral portion joined to a peripheral portion of the pixel substrate for sealing a space above the pixel substrate, wherein
the pixel substrate and the sealing substrate are joined and sealed at the peripheral portion by a metal joint solder layer which is formed by patterning,
the surfaces of the pixel substrate, the sealing substrate, or the pixel substrate and the sealing substrate have projections and depressions in a formation region of the joint solder layer, and
a mask film pattern is placed on each of the sides of the joint solder layer.
5. A display panel according to claim 4, wherein
the solder layer is formed directly on the pixel substrate, the sealing substrate, or the pixel substrate and the sealing substrate.
6. A display panel according to claim 4, further including
a metal layer formed on the pixel substrate, the sealing substrate, or the pixel substrate and the sealing substrate, and having a high adhesion property with the solder layer,
wherein the solder layer is formed on the metal layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A mixer with IQ gain-phase calibration circuit, comprising:
an I-path input stage, for receiving input voltage signals and converting said input voltage signals to current signals;
a Q-path input stage, for receiving input voltage signals and converting said input voltage signals to current signals;
an I-path switching stage, connected to said I-path input stage to receive said converted current signal and mixing said converted current signal with built-in local oscillators;
a Q-path switching stage, connected to said Q-path input stage to receive said converted current signal and mixing said converted current signal with built-in local oscillators; and
an output stage, said output stage further comprising a phase calibration module and and a gain calibration module;
wherein said respective mixed signals from said I-path switching stage and said Q-path switching stage being then passed to said phase calibration module for phase calibration, and then through said gain calibration module for gain calibration.
2. The mixer with IQ gain-phase calibration circuit as claimed in claim 1, wherein said phase calibration module performs computation of Qph\u2014cal=Q+\u03b1I*I Iph\u2014cal=I+\u03b1Q*Q, where Iph\u2014cal and Qph\u2014cal are I and Q signals after phase calibration respectively, I and Q represent I and Q signals before phase calibration respectively, and \u03b11 and \u03b1Q are factors selected to satisfy Qx=\u2212\u03b1I*Ix and Iy=\u2212\u03b1Q*Qy, where Qx, Qy, Ix, and Iy are component vectors of Q and I decomposed along two quadrature directions x and y, respectively,
3. The mixer with IQ gain-phase calibration circuit as claimed in claim 2, wherein said Iph\u2014cal and Qph\u2014cal resulted from said phase calibration module are passed to said gain calibration module, and said gain calibration module performs computation of Qgain\u2014cal=\u03b2Q*Qph\u2014cal and Igain\u2014cal=\u03b2I*Iph\u2014cal, where \u03b2I and \u03b2Q re selected factors, and then multiplies with a factor before outputting.
4. The mixer with IQ gain-phase calibration circuit as claimed in claim 1, wherein said phase calibration module and said gain calibration module are implemented at intermediate frequency avoid parasitic effect at high frequency.