1. An apparatus for centering a workpiece, comprising:
a centering tool which has a pair of action pads adapted to come into engagement with a circular part of the workpiece attracted to a chuck,
a support block having the action pads mounted thereon in a fashion that the action pads are spaced away from one another, and
a moving part to bear the support block for free turning on a fulcrum of the support block;
wherein the centering tool includes a support plate for the support block, and the pair of action pads made in a fashion raised above the support plate;
a shank fastened to a moving holder and mounted to the support plate to provide the fulcrum on which the support plate is allowed to turn freely, and
a stopper fastened to the shank so as to come into abutment against recessed edges that are in opposition to one another on both sides of the stopper, and
wherein as the moving part gets the fulcrum of the support block that moves towards a rotational center of the chuck, the action pads alternately come into engagement from any one side against the workpiece that is held at off-center relation in the chuck, thereby compensating the off-center of the workpiece to bring a center of the workpiece in alignment with the rotational center of the chuck.
2. An apparatus for centering a workpiece, as set forth in claim 1, wherein the chuck is a magnet chuck equipped on a machine tool to attract a cylindrical workpiece thereon and wherein the action pads are made to rise above the support block to come into an outside circular surfaces of the workpiece, performing a centering operation of the workpiece on the chuck.
3. An apparatus for centering a workpiece, as set forth in claim 1, wherein the moving part fastened to the shank extending out of the support block of the centering tool is a holder mounted on a turret equipped on a machine tool.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A delay element, comprising:
a variable delay element for generating a failure to lock signal, said variable delay element configured to be reset upon generation of said failure to lock signal; and
a static delay element connected in series with said variable delay element, said static delay element activated upon receipt of said failure to lock signal.
2. The delay element of claim 1 further comprising a reset signal for deactivating said static delay element.
3. The delay element of claim 1 wherein said variable delay element has a delay of:
N*tCK\u2212(D1\u2032+D2\u2032+tSD*) where
N is the slope of the Nth tCK loop within the variable delay element;
tCK is the cycle time of an input signal;
D1\u2032+D2\u2032 is the delay of a delay model; and
tSD* is an amount of static delay provided by said static delay element when activated.
4. A phase lock circuit, comprising:
a forward delay path having a variable delay portion connected in series with a static delay portion; and
a phase detector for comparing the phase of a reference signal and the phase of an output of said forward delay path, said phase detector generating a signal for controlling the amount of delay provided by said variable delay portion,
wherein said static delay element is configured to be activated and said variable delay portion is configured to be reset following a failure to lock the phase of said output of said forward delay path to a phase of said reference signal.
5. The phase lock circuit of claim 4 further comprising a reset signal for deactivating said static delay element.
6. The phase lock circuit of claim 4 further comprising a feedback path for generating a feedback signal responsive to said output of said forward delay path.
7. The phase lock circuit of claim 6 wherein said feedback path includes a delay model located between said output of said forward delay path and an input of said phase detector, said delay model operable to add a phase delay to said output signal.
8. The phase lock circuit of claim 4 wherein said variable delay path of said forward delay path has a delay of:
N*tCK\u2212(D1\u2032+D2\u2032+tSD*) where
N is the slope of the Nth tCK loop within the variable delay element;
tCK is the cycle time of an input signal;
D1\u2032+D2\u2032 is the delay of a delay model; and
tSD* is an amount of static delay provided by said static delay element when activated.
9. A method of locking the phase of an output signal to the phase of an input signal, comprising:
inputting an input signal to a variable delay element;
comparing a phase of an output signal of said variable delay element to a phase of said input signal;
adjusting the delay of said variable delay element until the phase of said output signal is locked to the phase of said input signal; and
in the event a lock is not achieved, activating a static delay element connected in series with said variable delay element, resetting said variable delay element, and repeating said comparing and adjusting.
10. The method of claim 9 wherein said variable delay element is controlled by shift left and shift right signals generated in response to said comparing of said output signal to said input signal.
11. The method of claim 10 wherein a failure to lock signal is generated upon generation of a last shift left signal.
12. The method of claim 9 wherein said variable delay element has a delay of:
N*tCK\u2212(D1\u2032+D2\u2032+tSD*) where
N is the slope of the Nth tCK loop within the variable delay element;
tCK is the cycle time of an input signal;
D1\u2032+D2\u2032 is the delay of a delay model; and
tSD* is an amount of static delay provided by said static element when activated.
13. A method of phase locking two signals, comprising:
inputting an input signal to a variable delay element;
comparing an output signal produced by said variable delay element to said input signal;
producing shift left and shift right signals in response to said comparing;
adjusting the delay of said variable delay element with said shift left and shift right signals until a lock is achieved between said output signal and said input signal; and
activating a static delay element connected in series with said variable delay element and resetting said variable delay element in the event the desired phase locking is not accomplished by the longest delay said variable delay element is capable of producing.
14. The method of claim 13 wherein a failure to lock signal is generated upon failure of the longest delay to achieve a phase lock between the two signals.
15. The method of claim 13 wherein said variable delay element has a delay of:
N*tCK\u2212(D1\u2032+D2\u2032+tSD*) where
N is the slope of the Nth tCK loop within the variable delay element;
tCK is the cycle time of an input signal;
D1\u2032+D2\u2032 is the delay of a delay model; and
tSD* is an amount of static delay provided by said static element when activated.