1-52. (canceled)
53. A method for determining a capacitance of a device used to hold a cell in an electrophysiological experiment, the method comprising:
applying a stimulus to the device through a force amplifier;
measuring a response to the stimulus with a separate sense amplifier; and
determining the capacitance of the device by analyzing the response to the stimulus.
54. The method of claim 53 further comprising employing compensation circuitry to compensate for the capacitance of the device.
55. The method of claim 53, wherein determining the capacitance of the device comprises calculating an RC time constant of the response to the stimulus.
56. A subsystem for determining a capacitance of a device used to hold a cell in an electrophysiological experiment, the subsystem comprising:
a force amplifier configured to apply a stimulus to the device;
a separate sense amplifier configured to measure a response to the stimulus; and
a determination module configured to determine the capacitance of the device by analyzing the response to the stimulus.
57. The subsystem of claim 56 further comprising compensation circuitry configured to compensate for the capacitance of the device.
58. The subsystem of claim 56, wherein the determination module is configured to calculate an RC time constant of the response to the stimulus in determining the capacitance of the device.
59-67. (canceled)
68. A method of compensating for a capacitive waveform present in a patch clamp system, comprising:
measuring a magnitude of the capacitive waveform at each of a plurality of times; and
outputting a gain-adjusted compensatory waveform from each of a plurality of compensation circuits to compensate for the capacitive waveform,
wherein each compensation circuit has a unique time constant.
69. The method of claim 68 further comprising outputting an unadjusted compensatory waveform from each of the plurality of compensation circuits.
70. The method of claim 69 further comprising measuring a magnitude of each unadjusted compensatory waveform at each of the plurality of times.
71. The method of claim 70 further comprising calculating a gain adjustment for each of the plurality of compensation circuits.
72. The method of claim 71, wherein each gain adjustment is calculated based on the measured magnitude of the capacitive waveform at each of the plurality of times and the measured magnitude of each unadjusted compensatory waveform at each of the plurality of times.
73. The method of claim 68 further comprising calculating a leakage resistance present in the patch clamp system.
74. The method of claim 73 further comprising adjusting the measurement of the capacitive waveform to account for a virtual peak to be introduced into the capacitive waveform following compensation of the leakage resistance.
75. The method of claim 73 further comprising compensating for the leakage resistance present in the patch clamp system.
76. The method of claim 75 further comprising re-measuring the magnitude of the capacitive waveform at each of the plurality of times while the leakage resistance is compensated for.
77. A subsystem for compensating for a capacitive waveform present in a patch clamp system, comprising:
measurement circuitry for measuring a magnitude of the capacitive waveform at each of a plurality of times; and
a plurality of compensation circuits, each compensation circuit having a unique time constant and configured to output a gain-adjusted compensatory waveform to compensate for the capacitive waveform.
78. The subsystem of claim 77, wherein each compensation circuit is further configured to output an unadjusted compensatory waveform.
79. The subsystem of claim 78, wherein the measurement circuitry is further configured to measure a magnitude of each unadjusted compensatory waveform at each of the plurality of times.
80. The subsystem of claim 79 further comprising calculation circuitry for calculating a gain adjustment for each of the plurality of compensation circuits.
81. The subsystem of claim 80, wherein each gain adjustment is calculated based on the measured magnitude of the capacitive waveform at each of the plurality of times and the measured magnitude of each unadjusted compensatory waveform at each of the plurality of times.
82. The subsystem of claim 77 further comprising calculation circuitry for calculating a leakage resistance present in the patch clamp system.
83. The subsystem of claim 82, wherein the calculation circuitry is further configured to adjust the measurement of the capacitive waveform to account for a virtual peak to be introduced into the capacitive waveform following compensation of the leakage resistance.
84. The subsystem of claim 82 further comprising leakage resistance compensation circuitry for compensating the leakage resistance present in the patch clamp system.
85. The subsystem of claim 84, wherein the measurement circuitry is further configured to re-measure the magnitude of the capacitive waveform at each of the plurality of times while the leakage resistance compensation circuitry compensates the leakage resistance.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit comprising:
a log amp to generate an envelope signal in response to an RF input signal; and
a translinear post-processing circuit coupled to the log amp to provide a measure of the envelope signal to extract an RMS value of the RF input signal;
where the translinear post-processing circuit comprises devices in a translinear loop having exponential characteristics.
2. The circuit of claim 1 where the log amp comprises a demodulating progressive compression log amp.
3. The circuit of claim 1 where the post-processing circuit implements a square-law function.
4. The circuit of claim 3 where the envelope signal is scaled in the logarithmic domain so the post-processing circuit provides a square-law response in a linear domain.
5. The circuit of claim 3 where the post-processing circuit implements an RMS function.
6. The circuit of claim 1 where the post-processing circuit comprises a translinear loop having a \u0394VBE element to introduce the envelope signal into the loop.
7. A circuit according to claim 1 where:
the translinear loop is arranged to provide a power measurement function; and
the devices in the translinear loop include a \u0394VBE element to introduce an input signal into the loop in the logarithmic domain.
8. The circuit of claim 7 where the translinear loop is arranged to implement an RMS function.
9. The circuit of claim 7 where the \u0394VBE element comprises a resistor connected in series in the loop.
10. The circuit of claim 9 where the input signal is applied to the resistor as a current.
11. The circuit of claim 10 where the circuit is arranged to cancel a pedestal in the input signal.
12. The circuit of claim 7 where the translinear loop comprises:
an input path having one or more junctions arranged to operate at a constant current; and
an output path having one or more transistors coupled to the input path and arranged to provide an output signal as a current.
13. The circuit of claim 12 where the translinear loop is arranged to provide a square-law signal in response to the input signal.
14. The circuit of claim 13 further comprising a capacitor to average the square-law signal.
15. The circuit of claim 14 further comprising a feedback loop coupled to the capacitor and the translinear loop to implement an implicit square-root function.
16. The circuit of claim 15 where:
the input path includes two transistors having two junctions facing a first direction in the translinear loop;
the output path includes two transistors having two junctions facing a second direction in the translinear loop; and
the feedback loop comprises a transconductance cell having an input coupled to the capacitor and an output coupled to force a current through one of the two transistors in the output path.
17. A method comprising:
generating a compressed envelope signal using a logarithmic amplifier in response to an RF input signal; and
post-processing the envelope signal to provide a decompressed measure of the power represented by the envelope signal to extract an RMS value of the RF input signal using a translinear post-processing circuit;
where said post-processing the envelope signal comprises applying the envelope signal to devices in a translinear loop having exponential characteristics.
18. The method of claim 17 where said generating the envelope signal comprises rectifying and filtering the RF input signal.
19. The method of claim 18 where said rectifying and filtering the RF input signal comprises applying the RF input signal to a diode coupled to a capacitor.
20. The method of claim 19 further comprising generating the envelope signal in a logarithmic domain.
21. The method of claim 20 where said post-processing the envelope signal comprises converting the signal in the logarithmic domain back to the linear domain.
22. The method of claim 21 further comprising scaling the envelope signal in the logarithmic domain, thereby providing a square-law function in the linear domain.