1. A semiconductor device, comprising:
a substrate;
an insulating layer formed on the substrate;
a fin formed on the insulating layer, the fin having a plurality of side surfaces, a top surface and a bottom surface;
an oxide layer formed over the top surface of the fin;
a nitride layer formed over the oxide layer; and
a gate formed on the insulating layer, the gate surrounding the plurality of side surfaces, the top surface and the bottom surface of the fin at a channel region of the semiconductor device.
2. The semiconductor device of claim 1, wherein the gate comprises a first gate electrode disposed on a first side of the fin and a second gate electrode disposed on a second side of the fin opposite the first side.
3. The semiconductor device of claim 2, wherein the gate comprises a third gate electrode surrounding the bottom surface of the fin.
4. The semiconductor device of claim 3, wherein the gate comprises a fourth gate electrode surrounding the top surface of the fin.
5. The semiconductor device of claim 1, further comprising:
a first dielectric layer formed around the plurality of side surfaces and the bottom surface of the fin.
6. The semiconductor device of claim 5, wherein the first dielectric layer has a thickness ranging from about 8 \u212b to about 50 \u212b.
7. The semiconductor device of claim 1, wherein
the oxide layer has a thickness ranging from about 20 \u212b to about 400 \u212b, and
the nitride layer has a thickness ranging from about 100 \u212b to about 800 \u212b.
8. The semiconductor device of claim 1, further comprising:
a source region and a drain region formed above the insulating layer and adjacent a respective first and second end of the fin, wherein the insulating later comprises a buried oxide layer and the fin comprises at least one of silicon or germanium.
9. A semiconductor device, comprising:
a substrate;
an insulating layer disposed on the substrate;
a conductive fin formed on the insulating layer, the conductive fin having a first end, a second end and a middle portion located between the first and second ends, wherein the first and second ends are disposed on the insulating layer and the middle portion is separated from the insulating layer;
at least one dielectric layer formed over a top surface of the conductive fin;
a gate dielectric layer formed on side surfaces and a bottom surface of the conductive fin; and
a gate formed on the insulating layer, the gate surrounding the gate dielectric layer formed on the side surfaces and bottom surface at the middle portion of the conductive fin and covering the at least one dielectric layer formed over the top surface at the middle portion of the conductive fin.
10. The semiconductor device of claim 9, wherein the gate comprises a first gate electrode disposed on a first side of the conductive fin and a second gate electrode disposed on an opposite side of the conductive fin.
11. The semiconductor device of claim 10, wherein the gate further comprises a third gate electrode disposed on a bottom side of the conductive fin.
12. The semiconductor device of claim 11, wherein the gate further comprises a fourth gate electrode disposed on a top side of the conductive fin.
13. The semiconductor device of claim 9, wherein the at least one dielectric layer comprises:
an oxide layer having a thickness ranging from about 20 \u212b to about 400 \u212b, and
a nitride layer having a thickness ranging from about 100 \u212b to about 800 \u212b.
14. The semiconductor device of claim 9, further comprising:
a source region and a drain region formed above the insulating layer and adjacent a respective first and second end of the fin, wherein the gate dielectric layer has a thickness ranging from about 8 \u212b to about 50 \u212b.
15. A semiconductor device, comprising:
a substrate;
an insulating layer formed on the substrate;
a fin formed on the insulating layer, the fin having a plurality of side surfaces, a top surface and a bottom surface;
a dielectric layer formed around the plurality of side surfaces and the bottom surface of the fin, the dielectric layer having a thickness ranging from about 20 \u212b to about 50 \u212b; and
a gate formed on the insulating layer, the gate surrounding the plurality of side surfaces, the top surface and the bottom surface of the fin at a channel region of the semiconductor device.
16. The semiconductor device of claim 15, further comprising:
an oxide layer formed over the top surface of the fin; and
a nitride layer formed over the oxide layer.
17. The semiconductor device of claim 15, further comprising:
a source region and a drain region formed above the insulating layer and adjacent a respective first and second end of the fin, wherein the insulating later comprises a buried oxide layer and the fin comprises at least one of silicon or germanium.
18. The semiconductor device of claim 15, wherein the gate comprises a first gate electrode disposed on a first side of the fin and a second gate electrode disposed on a second side of the fin opposite the first side.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit for measuring an inrush current of a power supply, the circuit comprising:
a rectifier which includes input terminals adapted to connect with an AC supply, and output terminals which supply a direct voltage;
a capacitor connected in parallel to the output terminals of the rectifier; and
an ammeter connected between the capacitor and the power supply;
wherein the capacitor is charged by the AC supply via the rectifier, the capacitor supplies energy to the power supply, and the ammeter measures the magnitude of the inrush current.
2. The circuit as described in claim 1, wherein the rectifier is a rectifier bridge.
3. The circuit as described in claim 1, wherein a resistor is coupled between one of the output terminals of the rectifier and one of the electrodes of the capacitor.
4. The circuit as described in claim 3, wherein a switch is coupled between the resistor and the capacitor to form a discharging circuit.
5. The circuit as described in claim 4, further comprising a multi-way switch to control the charging or discharging of the capacitor.
6. The circuit as described in claim 1, further comprising a switch to control the capacitor supplying energy to the power supply.
7. The circuit as described in claim 1, wherein a voltmeter is connected parallel to the capacitor for measuring the magnitude of the voltage of the capacitor.
8. A circuit for measuring an inrush current of a power supply, the circuit comprising:
an apparatus for storing electrical energy, the apparatus connected to the power supply;
a charging circuit for charging the apparatus;
an ammeter connected between the apparatus and the power supply for measuring the magnitude of the inrush current when the apparatus supplies said electrical energy to the power supply; and
a discharging circuit for discharging the remaining electrical energy of the apparatus.
9. The circuit as described in claim 8, wherein the apparatus is a capacitor.
10. The circuit as described in claim 9, wherein the charging circuit comprises a rectifier for transforming alternating current into direct current to charge the capacitor.
11. The circuit as described in claim 9, wherein a voltmeter is connected parallel to the capacitor for measuring the magnitude of voltage of the capacitor.
12. The circuit as described in claim 8, wherein the discharging circuit comprises a resistor and a switch.
13. The circuit as described in claim 8, further comprising a multi-way switch to control the charging or discharging of the apparatus.
14. The circuit as described in claim 8, further comprising a switch to control the apparatus supplying energy to the power supply.
15. A circuit assembly for measuring inrush current of a power supply, comprising:
a power supply to be measured;
a power source to provide available power to said power supply;
an intermediate apparatus electrically connectable between said power supply and said power source, and capable of reserving electrical energy from said power source when electrical connection thereof with said power source is established and releasing said electrical energy to said power supply when another electrical connection thereof with said power supply is established;
a switch means capable of selectively and exclusively establishing one of said electrical connection between said apparatus and said power source, and said another electrical connection between said apparatus and said power supply; and
measure means electrically connectable between said intermediate apparatus and said power supply for measuring inrush current input into said power supply.
16. The circuit assembly as described in claim 15, wherein said intermediate apparatus is a capacitor.
17. The circuit assembly as described in claim 15, wherein said measure means is an ammeter capable to measure said inrush current of said power supply when said apparatus is releasing said electrical energy to said power supply.