1. In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, a method of sensing a page of memory cells, comprising:
providing a page source line to each individual page;
coupling the source of each memory cell of each individual page to its page source line;
coupling the page source lines of individual pages to an aggregate node for connection to a source voltage control circuit for sensing operation;
coupling the drain of each memory cell of said page to an associated bit line; and
providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for sensing operation, wherein each said predetermined bit line voltage is referenced with respect to said aggregate node so as not to be affected by any voltage differences between said aggregate node and a ground reference.
2. The method of sensing as in claim 1, wherein said page source line is at a higher potential than that of said source voltage control circuit.
3. The method of sensing as in claim 1, wherein said source voltage control circuit is referenced with respect to said ground reference.
4. The method of sensing as in claim 1, wherein said providing a predetermined bit line voltage further comprises:
providing a bit line voltage clamp; and
generating a control voltage to control the bit line voltage clamp to clamp the bit line at the predetermined bit line voltage.
5. The method of sensing as in claim 4, wherein said generating a control voltage further comprises:
providing a reference current;
providing a predetermined resistor; and
generating the control voltage by passing the reference current across the predetermined resistor.
6. The method of sensing as in claim 4, wherein said providing a predetermined bit line voltage clamp includes:
providing a first transistor having a source, drain and control gate and having a diode voltage drop across the control gate and the source;
coupling a voltage supply to the drain of the first transistor;
coupling the associated bit line to the source of the first transistor; and
applying the control voltage to the control gate of the first transistor such that the control voltage has a value given by the predetermined bit line voltage plus the diode voltage drop.
7. The method of sensing as in claim 6, wherein said generating a control voltage further comprises:
providing a reference current;
providing a predetermined resistor;
providing a second transistor having a substantially similar diode voltage drop as that of the first transistor; and
generating the control voltage by summing the voltage drop across the second transistor and the voltage drop created by passing the reference current across the predetermined resistor.
8. The method of sensing as in claim 6, wherein said generating a control voltage further comprises:
providing a regulated reference voltage;
providing a DAC-controlled potential divider; and
generating the control voltage by dividing said regulated reference voltage using the DAC-controlled potential divider.
9. The method as in any one of claims 1\u20138, wherein each of said memory cells stores one bit of data.
10. The method as in any one of claims 1\u20138, wherein each of said memory cells stores more than one bit of data.
11. A non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, said memory device, comprising:
a page source line coupled to the source of each memory cell in a page;
an aggregate node coupled to individual page source lines;
a source voltage control circuit coupled via said aggregate node to a page source line of a selected page for memory operation;
an associated bit line coupled to the drain of each memory cell of said page; and
a bit line voltage supply for providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for sensing operation, wherein each said predetermined bit line voltage is referenced with respect to said aggregate node so as not to be affected by any voltage differences between said aggregate node and a ground reference.
12. The memory device as in claim 11, wherein said page source line is at a higher potential than that of said source voltage control circuit.
13. The memory device as in claim 11, wherein said source voltage control circuit is referenced with respect to said ground reference.
14. The memory device as in claim 11, wherein said bit line voltage supply further comprises:
a bit line voltage clamp; and
a control voltage generator for generating a control voltage to control the bit line voltage clamp to clamp the bit line at the predetermined bit line voltage.
15. The memory device as in claim 14, wherein said control voltage generator further comprises:
a reference current;
a predetermined resistor; and
the control voltage generated is a function of the reference current and the predetermined resistor.
16. The memory device as in claim 14, wherein said bit line voltage clamp includes:
a first transistor having a source, drain and control gate and having a diode voltage drop across the control gate and the source;
a voltage supply coupled to the drain of the first transistor;
the associated bit line coupled to the source of the first transistor; and
the control voltage applied to the control gate of the first transistor such that the control voltage has a value given by the predetermined bit line voltage plus the diode voltage drop.
17. The memory device as in claim 16, wherein said control voltage generator further comprises:
a reference current;
a predetermined resistor;
a second transistor having a substantially similar diode voltage drop as that of the first transistor; and
the control voltage generated is a function of the voltage drop across the second transistor and the voltage drop created by passing the reference current across the predetermined resistor.
18. The memory device as in claim 16, wherein said control voltage generator further comprises:
a regulated reference voltage;
a DAC-controlled potential divider; and
an output control voltage given by dividing said regulated reference voltage using the DAC-controlled potential divider.
19. The memory device as in any one of claims 11\u201318, wherein each of said memory cells stores one bit of data.
20. The memory device as in any one of claims 11\u201318, wherein each of said memory cells stores more than one bit of data.
21. In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, a method of sensing a page of memory cells, comprising:
providing a page source line;
coupling the source of each memory cell of said page to said page source line;
switching said page source line to a source voltage control circuit for sensing operation;
coupling the drain of each memory cell of said page to an associated bit line; and
providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for sensing operation, wherein each said predetermined bit line voltage is referenced with respect to said page source line of said page so as not to be affected by any voltage differences between the page source line and a ground reference.
22. The method of sensing as in claim 21, wherein said page source line is at a higher potential than that of said source voltage control circuit.
23. The method of sensing as in claim 21, wherein said source voltage control circuit is referenced with respect to said ground reference.
24. The method of sensing as in claim 21, wherein said providing a predetermined bit line voltage further comprises:
providing a bit line voltage clamp; and
generating a control voltage to control the bit line voltage clamp to clamp the bit line at the predetermined bit line voltage.
25. The method of sensing as in claim 24, wherein said generating a control voltage further comprises:
providing a reference current;
providing a predetermined resistor; and
generating the control voltage by passing the reference current across the predetermined resistor.
26. The method of sensing as in claim 24, wherein said providing a predetermined bit line voltage clamp includes:
providing a first transistor having a source, drain and control gate and having a diode voltage drop across the control gate and the source;
coupling a voltage supply to the drain of the first transistor;
coupling the bit line to the source of the first transistor; and
applying the control voltage to the control gate of the first transistor such that the control voltage has a value given by the predetermined bit line voltage plus the diode voltage drop.
27. The method of sensing as in claim 26, wherein said generating a control voltage further comprises:
providing a reference current;
providing a predetermined resistor;
providing a second transistor having a substantially similar diode voltage drop as that of the first transistor; and
generating the control voltage by summing the voltage drop across the second transistor and the voltage drop created by passing the reference current across the predetermined resistor.
28. The method of sensing as in claim 26, wherein said generating a control voltage further comprises:
providing a regulated reference voltage;
providing a DAC-controlled potential divider; and
generating the control voltage by dividing said regulated reference voltage using the DAC-controlled potential divider.
29. The method as in any one of claims 21\u201328, wherein each of said memory cells stores one bit of data.
30. The method as in any one of claims 21\u201328, wherein each of said memory cells stores more than one bit of data.
31. A non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, said memory device, comprising:
a page source line coupled to the source of each memory cell in a page;
a page source line multiplexor;
a source voltage control circuit coupled via said page source line multiplexor to a page source line of a selected page for memory operation;
an associated bit line coupled to the drain of each memory cell of said page; and
a bit line voltage supply for providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for sensing operation, wherein each said predetermined bit line voltage is referenced with respect to said page source line so as not to be affected by any voltage differences between said page source line and a ground reference.
32. The memory device as in claim 31, wherein said page source line is at a higher potential than that of said source voltage control circuit.
33. The memory device as in claim 31, wherein said source voltage control circuit is referenced with respect to said ground reference.
34. The memory device as in claim 31, wherein said bit line voltage supply further comprises:
a bit line voltage clamp; and
a control voltage generator for generating a control voltage to control the bit line voltage clamp to clamp the bit line at the predetermined bit line voltage.
35. The memory device as in claim 34, wherein said control voltage generator further comprises:
a reference current;
a predetermined resistor; and
the control voltage generated is a function of the reference current and the predetermined resistor.
36. The memory device as in claim 34, wherein said bit line voltage clamp includes:
a first transistor having a source, drain and control gate and having a diode voltage drop across the control gate and the source;
a voltage supply coupled to the drain of the first transistor;
the associated bit line coupled to the source of the first transistor; and
the control voltage applied to the control gate of the first transistor such that the control voltage has a value given by the predetermined bit line voltage plus the diode voltage drop.
37. The memory device as in claim 36, wherein said control voltage generator further comprises:
a reference current;
a predetermined resistor;
a second transistor having a substantially similar diode voltage drop as that of the first transistor; and
the control voltage generated is a function of the voltage drop across the second transistor and the voltage drop created by passing the reference current across the predetermined resistor.
38. The memory device as in claim 36, wherein said control voltage generator further comprises:
a regulated reference voltage;
a DAC-controlled potential divider; and
an output control voltage given by dividing said regulated reference voltage using the DAC-controlled potential divider.
39. The memory device as in any one of claims 31\u201338, wherein each of said memory cells stores one bit of data.
40. The memory device as in any one of claims 31\u201338, wherein each of said memory cells stores more than one bit of data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A rotor blade for use in a gas turbine engine, the rotor blade comprising:
a root portion having a cooling air supply passage;
an airfoil portion extending from the root portion to a blade tip;
a multiple pass serpentine flow cooling circuit formed within the airfoil portion, the serpentine flow cooling circuit including a first leg and a last leg, and a middle leg positioned in the serpentine flow direction between the first and the last legs, the middle leg having an upper portion formed of at least a single channel with trip strips located within the single channel and a lower portion having a plurality of cooling channels in fluid communication with the at least one single channel; and,
the cooling channels in the lower portion include a plurality of near wall cooling channels extending along the pressure side of the blade and a plurality of near wall cooling channels extending along the suction side of the blade.
2. The rotor blade of claim 1, and further comprising:
the serpentine flow circuit is a three pass serpentine flow circuit with the first leg on the leading edge of the blade, the second leg including an upper portion formed of a single channel and a lower portion formed from a plurality of near wall channels, and the third or last leg being a trailing edge channel.
3. A rotor blade for use in a gas turbine engine, the rotor blade comprising:
a root portion having a cooling air supply passage;
an airfoil portion extending from the root portion to a blade tip;
a multiple pass serpentine flow cooling circuit formed within the airfoil portion, the serpentine flow cooling circuit including a first leg and a last leg, and a middle leg positioned in the serpentine flow direction between the first and the last legs, the middle leg having an upper portion formed of at least a single channel with trip strips located within the single channel and a lower portion having a plurality of cooling channels in fluid communication with the at least one single channel;
a plurality of exit cooling holes located along the trailing edge of the blade and in fluid communication with the last leg to provide cooling air along the trailing edge of the blade;
the exit holes are metering holes and open into a diffusion hole;
a plurality of diffusion slots arranged along the trailing edge of the blade and opening onto the pressure side;
each diffusion slot being in fluid communication with a plurality of diffusion holes; and,
the diffusion slots each having a second diffuser in fluid communication with the diffusion holes, and a third diffusion located downstream from the second diffuser such that cooling air passes through a series of three diffusers before being discharge out from the blade.
4. A large turbine rotor blade for use in a gas turbine engine, the large turbine rotor blade comprising:
a root section;
an airfoil section extending from the root section;
a 3-pass serpentine flow cooling circuit to provide internal cooling for the airfoil section;
the 3-pass serpentine flow cooling circuit including a first leg located along a leading edge section of the airfoil and extending from the root section to a blade tip, a third leg located adjacent to a trailing edge section of the airfoil and extending from the root section to the blade tip;
the 3-pass serpentine flow cooling circuit including a second leg with an upper portion channel and a lower portion channel;
the upper portion channel is formed by a single channel that extends from a pressure side wall to a suction side wall of the airfoil;
the lower portion channel is formed by a plurality of near wall cooling channels formed in the pressure side wall of the airfoil and a plurality of near wall cooling channels formed in the suction side wall of the airfoil.
5. The large turbine rotor blade of claim 4, and further comprising:
a dead cavity formed between the pressure side near wall cooling channels and the suction side near wall cooling channels.
6. The large turbine rotor blade of claim 4, and further comprising:
a collection cavity located in the blade root, the collection cavity being in fluid communication with the plurality of near wall cooling channels and the third leg of the serpentine flow cooling circuit.
7. The large turbine rotor blade of claim 4, and further comprising:
the first and third legs of the serpentine flow cooling circuit both include trip strips on the wall surfaces to enhance heat transfer.
8. The large turbine rotor blade of claim 4, and further comprising:
A plurality of exit cooling holes located along the trailing edge of the blade and in fluid communication with the third leg to provide cooling air along the trailing edge of the blade;
the exit holes are metering holes and open into a diffusion hole;
a plurality of diffusion slots arranged along the trailing edge of the blade and opening onto the pressure side; and,
each diffusion slot being in fluid communication with a plurality of diffusion holes.
9. The large turbine rotor blade of claim 4, and further comprising:
the diffusion slots each having a second diffuser in fluid communication with the diffusion holes, and a third diffusion located downstream from the second diffuser such that cooling air passes through a series of three diffusers before being discharge out from the blade.