1. A light emitting device comprising:
a submount having first contacts separated by at least one first channel,
a light emitting structure having a metal layer with second contacts separated by at least one second channel, and
one or more elements added to the light emitting structure to reduce a thermally induced stress in the light emitting structure in a vicinity of the second channel,
wherein the one or more elements include one or more gaps in the metal layer, the gaps being situated to distribute the stress beyond the vicinity of the second channel.
2. The light emitting device of claim 1, wherein the one or more elements include a buffer layer between the metal layer and a light emitting element in the light emitting structure, the buffer layer having a higher compliancy than the metal layer.
3. The light emitting device of claim 2, wherein the buffer layer includes gold.
4. (canceled)
5. The light emitting device of claim 1, wherein the one or more elements include a filler material within the second channel, the filler material being selected based on its CTE.
6. The light emitting device of claim 1, wherein the one or more elements include a filler material within the first channel, the filler material being selected based on its CTE.
7. A light emitting device comprising:
a submount having first contacts separated by at least one first channel,
a light emitting structure having a metal layer with second contacts separated by at least one second channel, and
one or more elements added to the light emitting structure to reduce a thermally induced stress in the light emitting structure in a vicinity of the second channel,
wherein the light emitting structure is coupled to the submount by an interconnect material, and
the one or more elements include additional interconnect material in an area adjacent the second channel.
8. The light emitting device of claim 7, wherein the interconnect material includes a plurality of micro bumps.
9. The light emitting device of claim 1, wherein the light emitting structure comprises a flip chip structure.
10. The light emitting device of claim 7, wherein the metal layer comprises an alloy.
11. The light emitting device of claim 10, wherein the alloy includes a copper alloy.
12. The light emitting device of claim 11, wherein the copper alloy includes at least one of: CuNi, CuNiTi, CuW, CuFe, and CuMo.
13. The light emitting device of claim 11, wherein the copper alloy includes CuNiTi.
14. A light emitting device comprising:
a submount having first contacts separated by at least one first channel, and
a light emitting structure having a metal layer with second contacts separated by at least one second channel,
wherein the metal layer includes an alloy having a CTE that is less than a CTE of copper within a temperature range of 20-250\xb0 C.
15. The light emitting device of claim 14, wherein the alloy includes a copper alloy.
16. The light emitting device of claim 15, wherein the copper alloy includes at least one of: CuNi, CuNiTi, CuW, CuFe, and CuMo.
17. The light emitting device of claim 15, wherein the copper alloy includes CuNiTi.
18. The light emitting device of claim 14, wherein the CTE of the alloy is less than 10 ppmK within a temperature range of 20-250\xb0 C.
19. The light emitting device of claim 14, wherein the CTE of the alloy is less than 8 ppmK within a temperature range of 20-250\xb0 C.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a passivation film on a semiconductor substrate comprising forming a first silicon nitride containing layer on said substrate, oxidizing the surface of said first silicon nitride containing layer, and forming a second silicon nitride containing layer on the oxidized surface of said first silicon nitride containing layer.
2. A method as claimed in claim 1, wherein said surface of said first silicon nitride containing layer is oxidized by exposure to an oxygen-containing gas plasma.
3. A method as claimed in claim 2, wherein said oxygen-containing gas plasma comprises a nitrous oxide plasma.
4. A method as claimed in claim 1, wherein said surface of said first silicon nitride containing layer is oxidized by exposure to an oxygen containing gas.
5. A method as claimed in claim 1, wherein said first and second silicon nitride containing layers are formed using plasma enhanced chemical vapor deposition.
6. A method as claimed in claim 5, wherein said first and second silicon nitride containing layers are formed by providing a gas mixture comprising N2, SiH4 and, optionally, NH3 and energizing said gas mixture to create a gas plasma and form a silicon nitride containing layer on said semiconductor substrate.
7. A method as claimed in claim 6, wherein the flow rate of N2 is from between about 10 to about 20,000 sccm, the flow rate of SiH4 is from between about 10 to about 1000 sccm,
8. A method as claimed in claim 7, wherein said gas mixture includes NH3, and the flow rate of said NH3 is from between about 0.1 to about 1000 sccm.
9. A method as claimed in claim 6, wherein said energizing step takes place in a PECVD reaction chamber and comprises applying from between about 100 to about 1500 watts of RF power to said PECVD chamber while the chamber is maintained at a pressure of from between about 1 to about 50 Torr, and a temperature of from between about 100\xb0 to about 550\xb0 C.
10. A method as claimed in claim 1, wherein said first silicon nitride containing layer has a thickness of from between about 4000 to about 8000 angstroms, and said second silicon nitride containing layer has a thickness of from between about 4000 to about 8000 angstroms.
11. A method as claimed in claim 1, wherein said semiconductor substrate comprises a DRAM memory device.
12. A method of forming a passivation film on a semiconductor substrate, comprising forming a first silicon nitride containing layer on said semiconductor substrate, oxidizing the surface of said first silicon nitride containing layer by exposing said first silicon nitride containing layer to an oxygen-containing plasma, and forming a second silicon nitride containing layer on the oxidized surface of said first silicon nitride containing layer.
13. A method as claimed in claim 12, wherein said surface of said first silicon nitride containing layer is oxidized by exposure to an oxygen-containing gas plasma.
14. A method as claimed in claim 13, wherein said oxygen-containing gas plasma comprises a nitrous oxide plasma.
15. A method of forming a passivation film on a semiconductor substrate, comprising providing a semiconductor substrate in a reaction chamber, forming a first silicon nitride containing layer on said semiconductor substrate, oxidizing the surface of said first silicon nitride containing layer by exposing said first silicon nitride containing layer to an oxygen-containing plasma in said reaction chamber, and forming a second silicon nitride containing layer on the oxidized surface of said first silicon nitride containing layer.
16. A method as claimed in claim 15, wherein said oxygen-containing gas plasma comprises a nitrous oxide plasma.
17. A method of forming a passivation film on a semiconductor substrate, comprising providing a semiconductor substrate in a reaction chamber, exposing said semiconductor substrate to a first gas plasma comprising N2 and SiH4, forming a first silicon nitride containing layer on said semiconductor substrate, oxidizing the surface of said first silicon nitride containing layer by exposing said first silicon nitride containing layer to an oxygen-containing plasma in said reaction chamber, exposing said oxidized surface of said first silicon nitride containing layer to a second gas plasma comprising N2 and SiH4, and forming a second silicon nitride containing layer on the oxidized surface of said first silicon nitride containing layer.
18. A method as claimed in claim 17, wherein said oxygen-containing gas plasma comprises a nitrous oxide plasma.
19. A method as claimed in claim 17, wherein said first and second gas plasmas include NH3.
20. A method as claimed in claim 17, wherein said reaction chamber comprises a PECVD chamber.
21. A semiconductor device comprising a substrate and a passivation film on said substrate, wherein said passivation film comprises first and second silicon nitride containing layers and an oxidized interface between said first and second silicon nitride containing layers.
22. A semiconductor device as claimed in claim 21 wherein, said oxidized interface is formed by exposing the surface of said first silicon nitride containing layer to an oxygen-containing plasma.