1. A heat-sealing machine for heat-sealing an end part of a package containing a polymer battery module provided with a tab, said heat-sealing machine comprising a pair of sealing heads each provided with a sealing surface;
wherein the sealing surface of at least one of the sealing heads is provided with recess in a part thereof corresponding to the tab placed in the end part of the package.
2. The heat-sealing machine according to claim 1, wherein
both the sealing surfaces of the sealing heads are provided with recesses.
3. The heat-sealing machine according to claim 2, wherein
the recesses have a depth equal to about of thickness of the tab.
4. The heat-sealing machine according to claim 2, wherein
the recesses have a width in the range of w0.2 mm to w2.0 mm, where w is width of the tab.
5. The heat-sealing machine according to claim 1, wherein
the package is formed from a laminated structure including, as essential components, a base layer, an adhesive layer, a first chemical conversion coating, a barrier layer, a second chemical conversion coating and an innermost layer.
6. The heat-sealing machine according to claim 5, wherein
the innermost layer is a polyolefin resin film, and the innermost layer is bonded to the second chemical conversion coating by dry lamination.
7. The heat-sealing machine according to claim 5, wherein
the laminated structure further includes an acid-modified polyolefin resin layer sandwiched between the second chemical conversion coating and the innermost layer, the innermost layer is formed of a polypropylene resin, and the acid-modified polyolefin layer and the innermost layer formed of the polypropylene resin are laminated by hot lamination at a process temperature not lower than the softening point of the acid-modified polyolefin resin.
8. The heat-sealing machine according to claim 5, wherein
the laminated structure further includes an extruded resin layer of an acid-modified polyolefin resin sandwiched between the second chemical conversion coating and the innermost layer, the innermost layer is a polyolefin resin film, the extruded resin layer and the innermost layer are laminated to the second chemical conversion coating by sandwich lamination, and the laminated structure is heated at a temperature not lower than softening point of the acid-modified polyolefin resin.
9. The heat-sealing machine according to claim 5, wherein
the laminated structure further includes an extruded resin layer of an acid-modified polyolefin resin sandwiched between the second chemical conversion coating and the innermost layer, the innermost layer is formed of a polyolefin resin, the extruded resin layer and the innermost layer are laminated to the second chemical conversion coating by coextrusion, and the laminated structure is heated at a temperature not lower than softening point of the acid-modified polyolefin resin.
10. A heat-sealing method comprising the steps of:
putting a polymer battery module provided with a tab in a pouch package having one unsealed part through the unsealed part so that the tab is placed in the unsealed part of the pouch package; and
heat-sealing the unsealed part of the pouch package with a pair of sealing heads respectively having sealing surfaces, at least one of which being provided with a recess in a part corresponding to the tab.
11. A heat-sealing method comprising the steps of:
putting a polymer battery module provided with a tab in an embossed package; and
heat-sealing the embossed package with a pair of sealing heads respectively having sealing surfaces, at least one of which being provided with a recess in a part corresponding to the tab.
12. An embossing method of embossing a workpiece having a plurality of package sections by using an embossing machine provided with a male die part having male corrugated parts formed so as to correspond to boundary parts between the adjacent package sections of the workpiece, a male pressing part extending between the male corrugated parts and a male forming part placed in an opening formed in the male pressing part, and a female die part having female corrugated parts corresponding to the male corrugated parts, and a female pressing part provided with a forming recess corresponding to the male forming part, said embossing method comprising the steps of:
forming cuts in a part of each of the package sections of the workpiece corresponding to the male pressing part and the female pressing part; and
forming an embossed hollow part in each package section of the workpiece by embossing the workpiece with the male and the female die part.
13. The embossing method according to claim 12, wherein
the cuts are formed in the workpiece so that the cuts extends in a direction perpendicular to directions in which the workpiece is drawn during embossing.
14. The embossing method according to claim 12, wherein
the cuts are formed in each package section after the package section has been placed between the male and the female die part.
15. The embossing method according to claim 12, wherein
the cuts are formed in each package section before the package section is placed between the male and the female die part.
16. The embossing method according to claim 12, wherein
the workpiece is a laminated structure including, as essential components, a base layer, an aluminum layer and an adhesive layer.
17. A workpiece comprising a plurality of package sections, which is to be embossed by an embossing machine provided with a male die part having male corrugated parts formed so as to correspond to boundary parts between the adjacent package sections of the workpiece, a male pressing part extending between the male corrugated parts and provided with an opening, and a male forming part placed in the opening formed in the male pressing part, and a female die part having female corrugated parts corresponding to the male corrugated parts, and a female pressing part extending between the female corrugated parts and provided with a forming recess corresponding to the male forming part,
further comprising cuts in parts of each package section to be placed between the male pressing part and the female pressing part.
18. The workpiece according to claim 17, wherein
the workpiece is a laminated structure including, as essential components, a base layer, an aluminum layer and an adhesive layer.
19. A work pressing machine for pressing a part of a workpiece other than a part having an embossed hollow part formed by embossing of the workpiece, said workpiece pressing machine comprising:
a first die part provided with a recess for receiving the embossed part of the workpiece and disposed on one side of the workpiece, and
a second die part disposed on the other side of the workpiece to compress the workpiece between the first and the second die part;
wherein at least either the first or the second die part is heated.
20. The work pressing machine according to claim 19, wherein
both the first and the second die part are heated.
21. The work pressing machine according to claim 19, wherein
the workpiece is a laminated structure including, as essential components, a base layer, an aluminum layer and an adhesive layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An interface for use between a parallel bus and a serial bus, comprising:
a plurality of serializerdeserializer circuits that generate a clock signal, wherein one of said serializerdeserializer circuits is a master circuit generating a master clock signal and the remaining of said serializerdeserializer circuits are slave circuits generating slave clock signals, wherein said master clock signal is distributed to said slave circuits and wherein said master clock is substantially phase-aligned to a reference clock;
a clock divider associated with said master circuit for selectively generating a master clock signal having one or more lower data rates than said reference clock; and
a frequency detector associated with each of said slave circuits for automatically detecting a rate of said master clock signal.
2. The interface of claim 1, further comprising a data interleaver in each of said serializerdeserializer circuits to handle data interleaving for said lower data rates.
3. The interface of claim 1, wherein said master circuit generates a double rate clock having a rate that is twice the rate of said master clock and wherein said double rate clock is distributed to said slave circuits.
4. The interface of claim 1, wherein said slave circuits further comprise a multiplexer for selecting an appropriate clock signal based on rate identification information from said corresponding frequency detector.
5. The interface of claim 1, wherein selected data rate information is provided only to said master circuit.
6. The interface of claim 1, wherein said interface is configured to compensate for a clock skew by identifying a phase of said master clock
7. A method for use between a parallel bus and a serial bus, comprising:
generating a plurality of clock signals using a plurality of serializerdeserializer circuits, wherein one of said serializerdeserializer circuits is a master circuit generating a master clock signal and the remaining of said serializerdeserializer circuits are slave circuits generating slave clock signals;
distributing said master clock signal to said slave circuits and wherein said master clock is substantially phase-aligned to a reference clock;
selectively generating a master clock signal having one or more lower data rates than said reference clock using a clock divider associated with said master circuit; and
automatically detecting a rate of said master clock signal using a frequency detector associated with each of said slave circuits.
8. The method of claim 7, further comprising the step of performing data interleaving in each of said serializerdeserializer circuits for said lower data rates.
9. The method of claim 7, further comprising the steps of generating a double rate clock in said master circuit having a rate that is twice the rate of said master clock and distributing said double rate clock to said slave circuits.
10. The method of claim 7, further comprising the step of selecting an appropriate clock signal in said slave circuits based on rate identification information from said corresponding frequency detector.
11. The method of claim 7, further comprising the step of providing selected data rate information only to said master circuit.
12. The method of claim 7, further comprising the step of compensating for a clock skew by identifying a phase of said master clock
13. An integrated circuit, comprising:
an interface for use between a parallel bus and a serial bus, comprising:
a plurality of serializerdeserializer circuits that generate a clock signal, wherein one of said serializerdeserializer circuits is a master circuit generating a master clock signal and the remaining of said serializerdeserializer circuits are slave circuits generating slave clock signals, wherein said master clock signal is distributed to said slave circuits and wherein said master clock is substantially phase-aligned to a reference clock;
a clock divider associated with said master circuit for selectively generating a master clock signal having one or more lower data rates than said reference clock; and
a frequency detector associated with each of said slave circuits for automatically detecting a rate of said master clock signal.
14. The integrated circuit of claim 13, further comprising a data interleaver in each of said serializerdeserializer circuits to handle data interleaving for said lower data rates.
15. The integrated circuit of claim 13, wherein said master circuit generates a double rate clock having a rate that is twice the rate of said master clock and wherein said double rate clock is distributed to said slave circuits.
16. The integrated circuit of claim 13, wherein said slave circuits further comprise a multiplexer for selecting an appropriate clock signal based on rate identification information from said corresponding frequency detector.
17. The integrated circuit of claim 13, wherein selected data rate information is provided only to said master circuit.
18. The integrated circuit of claim 13, wherein said interface is configured to compensate for a clock skew by identifying a phase of said master clock