1. A class D amplifier comprising:
a driver circuit configured to amplify a PWM (pulse width modulation) signal to generate an amplified PWM signal; and
a reset circuit for applying a predetermined voltage at an input of the driver circuit for a time period after a power supply voltage for the class D amplifier is applied or before the power supply voltage is deactivated;
wherein the driver circuit includes:
a plurality of buffers for amplifying channel PWM signals to generate amplified channel PWM signals; and
a power output stage with power transistors having the amplified channel PWM signals applied thereon,
wherein the predetermined voltage of the reset circuit is applied at an input of one of the plurality of buffers that is coupled between the reset circuit and the power transistors.
2. The class D amplifier of claim 1, wherein
the power output stage includes a P-channel power transistor and an N-channel power transistor that are complementarily turned on depending on a logic state of the PWM signal.
3. The class D amplifier of claim 2, wherein the predetermined voltage from the reset circuit turns off the P-channel power transistor for the time period.
4. The class D amplifier of claim 2, wherein the predetermined voltage from the reset circuit turns on the N-channel power transistor for the time period.
5. The class D amplifier of claim 2, wherein the driver circuit includes:
a P-channel buffer for amplifying a P-channel PWM signal to generate an amplified P-channel PWM signal that is applied on a gate of the P-channel power transistor; and
an N-channel buffer for amplifying an N-channel PWM signal to generate an amplified N-channel PWM signal that is applied on a gate of the N-channel power transistor.
6. The class D amplifier of claim 5, wherein the reset circuit includes:
a switch coupled between an input of one of the P-channel and N-channel buffers and a voltage source generating the predetermined voltage; and
a reset signal source that turns on the switch for the time period.
7. The class D amplifier of claim 6, wherein the switch is a field effect transistor.
8. A class D amplifier comprising:
a driver circuit configured to amplify a PWM (pulse width modulation) signal to generate an amplified PWM signal;
a reset circuit for applying a predetermined voltage at an input of the driver circuit for a time period after a power supply voltage for the class D amplifier is applied or before the power supply voltage is deactivated;
a power output stage having a P-channel power transistor and an N-channel power transistor that are complementarily turned on depending on a logic state of the PWM signal;
wherein the driver circuit includes:
a P-channel buffer for amplifying a P-channel PWM signal to generate an amplified P-channel PWM signal that is applied on a gate of the P-channel power transistor; and
an N-channel buffer for amplifying an N-channel PWM signal to generate an amplified N-channel PWM signal that is applied on a gate of the N-channel power transistor; and
a delay controller for generating the P-channel and N-channel PWM signals each with a respective transition such that the P-channel and N-channel power transistors are not turned on simultaneously.
9. The class D amplifier of claim 8, wherein the time period is after the power supply voltage to the driver circuit is applied or before the power supply voltage to the delay controller is deactivated.
10. The class D amplifier of claim 9, wherein the time period is determined from when the power supply voltage reaches a predetermined threshold voltage.
11. An audio device comprising:
a PWM (pulse width modulation) processor that converts audio data into a PWM signal;
a class D amplifier including:
a driver circuit configured to amplify the PWM signal to generate an amplified PWM signal; and
a reset circuit for applying a predetermined voltage at an input of the driver circuit for a time period after a power supply voltage is applied to the class D amplifier or before the power supply voltage is deactivated;
wherein the driver circuit includes:
a plurality of buffers for amplifying channel PWM signals to generate amplified channel PWM signals; and
a power output stage with power transistors having the amplified channel PWM signals applied thereon,
wherein the predetermined voltage of the reset circuit is applied at an input of one of the plurality of buffers that is coupled between the reset circuit and the power transistors;
a low-pass filter for low-pass filtering the amplified PWM signal to provide an audio signal; and
a speaker for generating sound from the audio signal.
12. The audio device of claim 11, wherein
the power output stage includes a P-channel power transistor and an N-channel power transistor that are complementarily turned on depending on a logic state of the PWM signal.
13. The audio device of claim 12, wherein the predetermined voltage from the reset circuit turns off the P-channel power transistor for the time period.
14. The audio device of claim 12, wherein the predetermined voltage from the reset circuit turns on the N-channel power transistor for the time period.
15. The audio device of claim 12, wherein the driver circuit includes:
a P-channel buffer for amplifying a P-channel PWM signal to generate an amplified P-channel PWM signal that is applied on a gate of the P-channel power transistor; and
an N-channel buffer for amplifying an N-channel PWM signal to generate an amplified N-channel PWM signal that is applied on a gate of the N-channel power transistor.
16. The audio device of claim 15, wherein the reset circuit includes:
a switch coupled between an input of one of the N-channel and P-channel buffers and a voltage source generating the predetermined voltage; and
a reset signal source that turns on the switch for the time period.
17. The audio device of claim 16, wherein the switch is a field effect transistor.
18. The audio device of claim 15, wherein the class D amplifier further includes:
a delay controller for generating the P-channel and N-channel PWM signals each with a respective transition such that the P-channel and N-channel power transistors are not turned on simultaneously.
19. The audio device of claim 18, wherein the time period is after the power supply voltage to the driver circuit is applied or before the power supply voltage to the delay controller is deactivated.
20. The audio device of claim 19, wherein the time period is determined from when the power supply voltage reaches a predetermined threshold voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An inductor apparatus comprising:
a substrate including an electrical insulation property and a non-magnetic material; and
a plurality of inductors disposed in the substrate so as to extend from a first surface of the substrate to a second surface of the substrate, each of the plurality of inductors including:
an inductor conductive part that has an electrical conductivity and extends in a thickness direction of the substrate; and
a magnetic layer that covers a side of the inductor conductive part and include a relative permeability and a soft magnetic material.
2. The inductor apparatus according to claim 1, wherein the relative permeability is 5000 or more.
3. The inductor apparatus according to claim 1, wherein a resistivity of the magnetic layer is 10 times or more a resistivity of the inductor conductive part.
4. The inductor apparatus according to claim 1, wherein a thickness of the magnetic layer is 10 \u03bcm or less.
5. The inductor apparatus according to claim 1, wherein a coercive force of the magnetic layer is 2 Am or less.
6. The inductor apparatus according to claim 1, wherein a saturation magnetization of the magnetic layer is 0.8 T or more.
7. The inductor apparatus according to claim 1, further comprising:
a connection conductive layer that is disposed on the second surface of the substrate and electrically couples one end of each of the inductor conductive parts in parallel.
8. The inductor apparatus according to claim 1, wherein the plurality of inductors are disposed in a thickness direction of the substrate via a part of the substrate.
9. The inductor apparatus according to claim 1, further comprising:
a conductive part on which a magnetic layer is not formed on one side of the plurality of inductors.
10. An inductor apparatus manufacturing method comprising:
forming magnetic layers of a soft magnetic material on sides of a plurality of inductor conductive parts that are vertically long and have an electrical conductivity to form a plurality of inductors;
heat-treating the plurality of inductors;
disposing the plurality of inductors aliening a longitudinal direction with a spacing;
injecting a resin including an electrical insulation property and a non-magnetic material between the plurality of inductors; and
curing the resin to form a substrate that supports the plurality of inductors.
11. The inductor apparatus manufacturing method according to claim 10,
wherein the heat-treating is performed such that the magnetic layers of the plurality of inductors have a relative permeability of 5000 or more.
12. An inductor apparatus manufacturing method comprising:
machining an electrically conductive block to form a plate-like connection conductive layer and a plurality of inductor conductive parts on a surface of the connection conductive layer so as to extend outward from the surface of the connection conductive layer;
forming magnetic layers including a soft magnetic material on sides of the plurality of inductor conductive parts to form a plurality of inductors;
heat-treating the plurality of inductors;
injecting a resin including an electrical insulation property and a non-magnetic material between the plurality of inductors; and
curing the resin to form a substrate that supports the plurality of inductors.
13. The inductor apparatus manufacturing method according to claim 12, wherein the heat-treating is performed such that the magnetic layers of the plurality of inductors have a relative permeability of 5000 or more.