1460735816-5e22a508-2344-49f2-9745-56491e51ab39

1. A semiconductor memory device including a plurality of memory cells,
wherein, when the semiconductor memory device enters a refresh mode, retention times of the memory cells are measured by a control circuit with respect to data patterns which are stored in the memory cells at the time of entry into the refresh mode,
wherein the memory cells are arranged in a matrix fashion to form a sub memory cell array, said sub memory cell array comprising a check word line and a data saving word line, and
wherein memory cell data on the check word line is copied through sense amplifiers to memory cells on the data saving word line.
2. The semiconductor memory device according to claim 1, wherein a plurality of refresh cycles corresponding to the retention times are set and a refresh operation is performed according to the refresh cycles.
3. The semiconductor memory device according to claim 2, wherein the refresh cycles include a short cycle T and a long cycle nT corresponding to n times the short cycle T, n being an integer greater than or equal to two.
4. The semiconductor memory device according to claim 1, wherein memory cell data on the data saving word line are copied back to the memory cells on the check word line.
5. The semiconductor memory device according to claim 1, wherein the memory cells on the data saving word line are subjected to short-cycle refreshing while the check word line is subjected to long-cycle refreshing, the memory cell data on the data saving word line being thereafter compared with the memory cell data on the check word line.
6. The semiconductor memory device according to claim 5, wherein the long-cycle refreshing or the short-cycle refreshing is set for each word line of the sub memory cell array with reference to the result of comparison and refreshing is performed.
7. The semiconductor memory device according to claim 6, wherein each word line of the sub memory cell array is refreshed at a first instant, and each word line set for short cycle refreshing is refreshed after a lapse of a short cycle T, while each word line set for long cycle refreshing is refreshed only after a lapse of a long cycle nT, corresponding to n times the first time T, wherein n is an integer greater than or equal to 2.
8. The semiconductor memory device according to claim 6, wherein short cycle refreshing is set for each word line of the sub memory cell array for which an error is detected as the result of comparison, and long cycle refreshing is set for each word line of the sub memory cell array for which no error is detected as the result of comparison.
9. The semiconductor memory device according to claim 1, wherein the sub memory cell array includes a data saving memory cell array having the data saving word line.
10. The semiconductor memory device according to claim 9, further comprising a comparator circuit for comparing data of the memory cells on a check word line to be subjected to measurement of the retention times and data of memory cells on the data saving word line.
11. The semiconductor memory device according to claim 9, further comprising a comparator circuit for comparing output data of registers for holding data of the memory cells on a check word line to be subjected to measurement of the retention times and output data from data amplifiers for outputting data of memory cells on the data saving word line.
12. The semiconductor memory device according to claim 11, further comprising a retention judging circuit for judging the retention time of the check word line with reference to output information from the comparator circuit, the output information representing coincidenceincoincidence for the memory cells on the check word line.
13. The semiconductor memory device according to claim 12, further comprising a refresh cycle setting register for holding a refresh cycle setting signal from the retention judging circuit.
14. The semiconductor memory device according to claim 9, wherein the data saving word line is provided by selecting a redundancy word line of a redundancy circuit.
15. A method of refreshing a semiconductor memory device, the method comprising:
making the semiconductor memory device enter a refresh mode;
measuring retention times of memory cells for each word line with respect to data patterns which are stored in the memory cells;
setting a plurality of refresh cycles corresponding to the retention times;
carrying out a refresh operation according to the refresh cycles; and
copying memory cell data on a check word line of the sub memory cell array into memory cells on a data saving word line.
16. The method according to claim 15, wherein the refresh cycles include a short cycle T and a long cycle nT corresponding to n times the short cycle T, n being an integer greater than or equal to two.
17. The method according to claim 15, the semiconductor memory device including a sub memory cell array comprising the memory cells arranged in a matrix fashion, the method further comprising:
long-cycle refreshing the check word line and the data saving word line;
short-cycle refreshing the data saving word line;
reading the memory cell data on the check word line and storing the memory cell data into registers; and
comparing the memory cell data on the data saving word line and the memory cell data read from the check word line and stored in the registers.
18. The method according to claim 17, further comprising setting long cycle refreshing or short cycle refreshing for each word line in the sub memory cell array in reference to the result of comparison.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An RFID tag configured to receive an RFID Activation command structure that is transmitted from an RFID reader and processed in the RFID tag,
the RFID tag comprising:
an antenna;
circuitry coupled to the antenna, the circuitry being configured to process the command structure;

the command structure comprising:
a plurality of fields, the plurality of fields comprising:
a sessioninventory flag identification field that specifies a session that the RFID reader will use after the RFID tag has been activated;
a field that indicates whether the RFID tag is to check a hibernate mode state of a sessioninventory flag as a parameter upon which to base activation of the RFID tag;
a control field that specifies if tag session locking is to be in effect after activation of the RFID tag; and
a value that places the RFID tag in a tag session locked mode to prevent a response to a normal mode command with a differing session code than one indicated in the Activation command structure,
wherein the sessioninventory flag state is controlled by an RFID reader programmable timer while in a hibernate mode,
wherein an activation of the RFID tag based on the timer controlled sessioninventory flag state is related to system transmit power control operations such that the RFID tag accessed at a lower reader transmit power level temporarily does not respond to reader commands transmitted at a higher power level.
2. The RFID tag of claim 1 wherein the command structure further comprises a reader lock field that indicates if the RFID tag is operable to utilizes tag-to-reader locking with the first RFID reader after the at least one RFID tag has been activated.
3. The RFID tag of claim 1 wherein the command structure further comprises at least one duty cycle field, within the plurality of fields, that specifies a duty cycle of operation of a receiver within the activated RFID tag.
4. The RFID tag of claim 1 wherein a state machine operation is altered when the RFID tag is locked onto a first RFID reader, the altered state machine operation causing the activated RFID tag to ignore a command from a second RFID reader that does not feature an appropriate identification in the reader identification code field.
5. The RFID tag of claim 4 wherein a specialized reader command is provided that overrides the lock between the RFID tag and the first RFID reader and returns the RFID tag to a hibernate mode.
6. The RFID tag of claim 1 wherein the RFID tag is configured to check a hibernate mode tag-to-reader locking flag to identify whether the RFID tag locks to the first RFID reader while in the hibernate mode.
7. The RFID tag of claim 6 wherein the hibernate mode tag-to-reader locking flag is the same flag as a normal mode tag-to-reader locking flag.
8. The RFID tag of claim 1 wherein a tag state machine operation is altered from a passive tag operation mode into an interference rejecting mode when at least one RFID tag is in a session locked mode with a first RFID reader, the altered state machine operation causing the at least one RFID tag to ignore a command from a second RFID reader that does not feature an appropriate identification in a session field of said command.
9. The RFID tag of claim 8 wherein a specialized reader command is provided that overrides the locked tag session between the at least one RFID tag and the first RFID reader and returns the at least one RFID tag to a hibernate mode.
10. The RFID tag of claim 1 wherein the command structure further comprises at least one duty cycle field, within the plurality of fields, that describes a subsequent duty cycle of operation of the RFID tag when the RFID tag is activated.
11. An RFID reader configured to generate an RFID Activation command structure that is transmitted from the REED reader to an RFID tag,
the RFID tag comprising:
an antenna;
circuitry coupled to the antenna, the circuitry being configured to generate the command structure;