What is claimed is:
1. A method for etching oxide during transistor fabrication, comprising the steps of:
(a) depositing a oxide on a substrate;
(b) depositing a mask over a portion of the oxide; and
(c) performing a combination drywet-etch to remove the oxide uncovered by the mask, thereby minimizing oxide undercut.
2. The method of claim 1 wherein step (c) further includes the step of:
(i) performing a low-energy dry-etch to remove a portion of the oxide.
3. The method of claim 2 wherein step (c) further includes the step of:
(ii) performing a brief wet-etch to remove any remaining oxide.
4. The method of claim 3 wherein step (c) further includes the step of:
(iii) performing the brief wet-etch for approximately 20 seconds.
5. The method of claim 4 wherein step (c)(i) further includes the step of:
(c)(i)(1) performing the low-energy dry-etch at less than approximately 200 electron volts.
6. A system for etching gate oxide during transistor fabrication, comprising the steps of:
means for depositing a gate oxide on a substrate;
means for depositing a tunnel oxide mask over a portion of the gate oxide; and
means for performing a combination drywet-etch to remove the gate oxide uncovered by the tunnel oxide mask, thereby minimizing tunnel oxide undercut.
7. The system of claim 6 wherein the combination drywet-etch includes a low-energy dry-etch that removes a portion of the gate oxide.
8. The system of claim 7 wherein the combination drywet-etch includes a brief wet-etch to remove any remaining gate oxide.
9. The system of claim 8 wherein the brief wet-etch is performed for approximately 20 seconds.
10. The system of claim 9 wherein the low-energy dry-etch is performed at less than approximately 200 electron volts.
11. A method for reducing gate oxide undercut, comprising the steps of:
(a) depositing a gate oxide on a substrate;
(b) depositing a tunnel oxide mask over a portion of the gate oxide; and
(c) performing a combination drywet-etch to remove the gate oxide uncovered by the tunnel oxide mask, the combination drywet-etch including the steps of,
(i) performing dry-etch at less than approximately 200 electron volts to remove approximately two thirds of the gate oxide, and
(ii) performing a wet-etch for a time sufficient to remove any remaining gate oxide, thereby minimizing tunnel oxide undercut.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing alignment mark of semiconductor device, the method comprising the steps of:
sequentially forming a pad oxide film and a pad nitride film on a semiconductor substrate;
selectively etching the pad nitride film and the pad oxide film to form a pad nitride film pattern and a pad oxide film pattern exposing a predetermined portion of the semiconductor substrate;
etching the semiconductor substrate using the pad nitride film pattern as a mask to form an alignment mark trench having a predetermined depth;
forming an oxide film for device isolation film filling the alignment mark trench on the entire surface;
planarizing the oxide film for device isolation film until the pad nitride film pattern is exposed to form a device isolation film; and
etching a predetermined thickness of the device isolation film to form an alignment mark prior to removing the pad nitride film pattern.
2. The method according to claim 1, wherein the depth of the alignment mark trench ranges from 2000 to 10000 \u212b.
3. The method according to claim 1, wherein the pad nitride film has a thickness ranging from 300 to 2000 \u212b.
4. The method according to claim 1, wherein the oxide film for device isolation film has a thickness ranging from 4000 to 15000 \u212b.
5. The method according to claim 1, wherein the step of planarizing the oxide film for device isolation film comprises a CMP process using a high selectivity slurry having a selectivity ratio of nitride film to oxide film ranging from 1:10 to 1:200.
6. The method according to claim 1, wherein the thickness of the pad nitride film pattern after planarizing the oxide film for device isolation film ranges from 200 to 10000 \u212b.
7. The method according to claim 6, wherein the removing the pad nitride film pattern comprises a cleaning process using phosphoric acid.