1. An automatic focusing method comprising:
determining a manner for auto focusing among at least an electromyogram signal manner and an ultrasonic image manner, wherein the electromyogram signal manner comprises a manner for calculating a distance to an object based on an electromyogram signal generated from an eyeball and the ultrasonic image manner comprises a manner for calculating a distance to an object based on at least one ultrasonic image of the eyeball;
calculating a distance from an eyeball of a user to an object at which the eyeball of the user looks according to the determined manner; and
adjusting, based on the calculated distance, a plane of focus including the object.
2. The automatic focusing method of claim 1, wherein calculating the distance comprises:
detecting the electromyogram signal generated from the eyeball; and
generating distance data based on the electromyogram signal.
3. The automatic focusing method of claim 1, wherein calculating the distance comprises:
collecting the ultrasonic images generated by ultrasonic imaging of the eyeball;
identifying a crystalline lens of the eyeball based on the ultrasonic images;
generating oblateness data by recognizing oblateness of the crystalline lens; and
generating distance data based on the oblateness data.
4. The automatic focusing method of claim 1, further comprising:
priorly providing an image including the plane of focus to the user.
5. The automatic focusing method of claim 4, wherein priorly providing the image including the plane of focus to the user comprises:
converting the image based on the plane of focus and a preset depth of field; and
providing the converted image to the user.
6. The automatic focusing method of claim 1, further comprising:
receiving a user input for automatic focusing.
7. The automatic focusing method of claim 6, wherein receiving the user input comprises:
detecting that the eyeball approaches a viewfinder.
8. The automatic focusing method of claim 6, wherein:
determining the manner for auto focusing comprises determining that the manner is the electromyogram signal manner,
wherein calculating the distance comprises detecting the electromyogram signal and generating distance data based on the electromyogram signal.
9. The automatic focusing method of claim 8, wherein:
determining the manner for auto focusing comprises determining that the manner is the ultrasonic image manner; and
calculating the distance comprises:
collecting the ultrasonic images by ultrasonic imaging of the eyeball;
identifying the crystalline lens included in the eyeball based on the ultrasonic images;
generating oblateness data by recognizing oblateness of the crystalline lens; and
generating distance data based on the oblateness data.
10. An automatic focusing apparatus comprising:
an eyeball measurement unit configured to detect a change generated in an eyeball of a user; and
a controller configured to:
determine a manner for auto focusing among at least electromyogram signal manner and ultrasonic image manner, wherein the electromyogram signal manner comprises a manner for calculating a distance to an object based on an electromyogram signal generated from an eyeball and the ultrasonic image manner comprises a manner for calculating a distance to an object based on at least one ultrasonic image of the eyeball;
calculate a distance from the eyeball of the user to an object at which the eyeball of the user looks according to the determined manner, and
adjust, based on the calculated distance, a plane of focus including the object.
11. The automatic focusing apparatus of claim 10, wherein the eyeball measurement unit comprises an electromyogram sensor configured to detect the electromyogram signal generated from the eyeball, and the controller is configured to generate the distance data based on the electromyogram signal.
12. The automatic focusing apparatus of claim 10, wherein the eyeball measurement unit comprises an ultrasonographic sensor configured to perform ultrasonic imaging of the eyeball and collect the ultrasonic images generated by ultrasonic imaging of the eyeball, and the controller is configured to identify a crystalline lens of the eyeball based on the ultrasonic images, generates oblateness data by recognizing oblateness of the crystalline lens, and generate distance data based on the oblateness data.
13. The automatic focusing apparatus of claim 10, further comprising:
a display unit configured to priorly provide an image including the plane of focus.
14. The automatic focusing apparatus of claim 13, wherein the controller is configured to convert the image based on the plane of focus and a preset depth of field and to control the display unit to provide the converted image to the user.
15. The automatic focusing apparatus of claim 14, wherein the display unit comprises a viewfinder, and the controller is configured to determine that a user input for automatic focusing is input when it is detected that the eyeball approaches the viewfinder.
16. The automatic focusing apparatus of claim 15, wherein the controller is configured to determine that the manner for auto focusing is the electromyogram signal manner and control an electromyogram sensor that is included in the eyeball measurement unit to detect an electromyogram signal generated from the eyeball.
17. The automatic focusing apparatus of claim 16, wherein the controller is configured to determine that the manner for auto focusing is the ultrasonic image manner, and collect the ultrasonic images generated by ultrasonic imaging of the eyeball by using an ultrasonographic sensor included in the eyeball measurement unit.
18. The automatic focusing apparatus of claim 10, wherein the controller is configured to detect a user input for automatic focusing before generating the distance data.
19. The automatic focusing apparatus of claim 10, wherein the controller is configured to provide automatic focusing for an electronic device including a camera.
20. The automatic focusing method of claim 1, further comprising providing automatic focusing for an electronic device including a camera.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory device, comprising:
a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate;
a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells; and
a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells,
wherein, the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells is replaced with a dummy memory cell from among the second plurality of dummy memory cells.
2. The device of claim 1, wherein the second plurality of dummy memory cells comprise:
a second plurality of drain dummy memory cells electrically coupled to bit lines through drain select transistors; and
a second plurality of source dummy memory cells electrically coupled to a common source line through source select transistors,
wherein the first plurality of normal memory cells are electrically coupled between the drain dummy memory cells and the source dummy memory cells.
3. The device of claim 2, wherein each of the at least one bad memory cell is replaced with a source dummy memory cell.
4. The device of claim 2, wherein each of the at least one bad memory cell is replaced with a source dummy memory cell adjacent to the first plurality of normal memory cells.
5. The device of claim 1, further comprising a peripheral circuit configured to control the operation of the first plurality of normal word lines and the second plurality of dummy word lines.
6. The device of claim 5, wherein, when a program operation is performed, the peripheral circuit is configured to apply a voltage to a normal word line that are electrically coupled to the at least one bad memory cell that is substantially the same as the voltage applied to a non-selected normal word line from among the first plurality of normal word lines.
7. The device of claim 5, wherein, when a read operation is performed, the peripheral circuit is configured to apply a voltage to a normal word line that are electrically coupled to the at least one bad memory cell that is substantially the same as the voltage applied to a non-selected normal word line from among the first plurality of normal word lines.
8. The device of claim 5, wherein, when an erase operation is performed, the peripheral circuit is configured to apply a ground voltage to a normal word line that are electrically coupled to the at least one bad memory cell.
9. A semiconductor memory device, comprising:
a plurality of cell strings electrically coupled to a plurality of drain select lines, respectively, the plurality of drain select lines extending in a row direction and arranged in a column direction, each of the plurality of cell strings including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate;
a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells; and
a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells,
wherein, the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cell is replaced with a dummy memory cell from among the second plurality of dummy memory cells.
10. The device of claim 9, wherein the at least one bad memory cell is included in a first cell string from among the plurality of cell strings,
a first bad memory cell from among the at least one bad memory cell is replaced with a dummy memory cell of the first cell string, and
a second bad memory cell from among the at least one bad memory cell is replaced with a dummy memory cell of a second cell string from among the plurality of cell strings.
11. The device of claim 9, wherein the at least one bad memory cell is included in a first cell string from among the plurality of cell strings,
a first bad memory cell from among the at least one bad memory cell is replaced with a dummy memory cell of a second cell string from among the plurality of cell strings, and
a second bad memory cell among the at least one bad memory cell is replaced with a dummy memory cell of a third cell string from among the plurality of cell strings.
12. The device of claim 9, wherein the second plurality of dummy memory cells of each of the plurality of cell strings include:
a second plurality of drain dummy memory cells electrically coupled to bit lines through drain select transistors; and
a second plurality of source dummy memory cells electrically coupled to a common source line through source select transistors,
wherein the first plurality of normal memory cells are electrically coupled between the drain dummy memory cells and the source dummy memory cells.
13. The device of claim 12, wherein a source dummy memory cell adjacent to the first plurality of normal memory cells from among the source dummy memory cells of each cell string is provided as a spare cell for replacing the at least one bad memory cell.
14. The device of claim 12, wherein the at least one bad memory cell is included in a first cell string from among the plurality of cell strings,
a first bad memory cell from among the at least one bad memory cell is replaced with the spare cell of the first cell string, and
a second bad memory cell from among the at least one bad memory cell is replaced with the spare cell of a second cell string from among the plurality of cell strings.
15. The device of claim 12, wherein the at least one bad memory cell is included in a first cell string from among the plurality of cell strings,
a first bad memory cell from among the at least one bad memory cell is replaced with the spare cell of a second cell string from among the plurality of cell strings, and
a second bad memory cell among the at least one bad memory cell is replaced with the spare cell of a third cell string from among the plurality of cell strings.
16. A memory system, comprising:
a semiconductor memory device; and
a controller configured to control at least one operation of the semiconductor memory device,
wherein the semiconductor memory device comprises:
a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked over a substrate;
a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells; and
second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells,
wherein, the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells are replaced with a dummy memory cell from among the second plurality of dummy memory cells.
17. The system of claim 16, wherein the second plurality of dummy memory cells comprise:
drain dummy memory cells electrically coupled to bit lines through drain select transistors; and
source dummy memory cells electrically coupled to a common source line through source select transistors,
wherein the first plurality of normal memory cells are electrically coupled between the drain dummy memory cells and the source dummy memory cells.
18. The system of claim 17, wherein each of the at least one bad memory cells is replaced with a source dummy memory cell.
19. The system of claim 17, wherein each of the at least one bad memory cells is replaced with a source dummy memory cell adjacent to the first plurality of normal memory cells.
20. The system of claim 16, wherein the controller is configured to convert a logical address received from an external device into a physical address that indicates a dummy memory cell from among the plurality of dummy memory cells.