1. A dry-sump lubrication type four-stroke cycle engine comprising:
a crankcase in which a crank chamber is formed in its front part and a transmission chamber is formed in its rear part, the crankcase having a pair of end walls positioned at one end and other end along a crank axis direction, respectively;
a first cover and a second cover disposed on the end walls of the crankcase, respectively; and
a first chamber and a second chamber formed in the first cover and the second cover, respectively,
wherein a partition wall of a given height is provided between the crank chamber and the transmission chamber so as to form an oil reservoir chamber in a lower part of the transmission chamber separated from the crank chamber by the partition wall,
wherein one of the end walls is provided with a drain passage through which oil drains from the crank chamber into the first chamber,
wherein the second chamber has a second oil reservoir chamber which communicates with the oil reservoir chamber so that a level of oil contained in the second oil reservoir chamber is equal to a level of oil in the oil reservoir chamber, and
wherein the engine further comprising a scavenging pump pumping up oil from the first chamber and discharges oil into the oil reservoir chamber or the second oil reservoir chamber.
2. The dry-sump lubrication type four-stroke cycle engine according to claim 1, wherein the first and the second chamber are connected by an oil passage,
wherein the scavenging pump is disposed in the second chamber, and a suction port of the scavenging pump is connected to one end of the oil passage to suck oil directly from the first chamber.
3. The dry-sump lubrication type four-stroke cycle engine according to claim 2, wherein the oil passage is formed below the drain passage connecting the crank chamber to the first chamber so as to extend under the crank chamber across the crankcase.
4. The dry-sump lubrication type four-stroke cycle engine according to claim 3, wherein the oil passage is formed integrally with the crankcase.
5. The dry-sump lubrication type four-stroke cycle engine according to claim 2, wherein the scavenging pump is placed in the second chamber so as to position a rotor thereof below a predetermined oil level in the second oil reservoir chamber.
6. The dry-sump lubrication type four-stroke cycle engine according to claim 5, wherein the scavenging pump placed in the second chamber is sealed so that oil is unable to flow in a reverse direction from the second chamber.
7. The dry-sump lubrication type four-stroke cycle engine according to claim 2, wherein the scavenging pump has a discharge opening at a level above a level of oil in the second chamber to discharge oil into air.
8. The dry-sump lubrication type four-stroke cycle engine according to claim 2, wherein a flat filter is placed in the oil passage.
9. The dry-sump lubrication type four-stroke cycle engine according to claim 1, wherein a generator of the engine is placed in the first chamber communicating with the crank chamber, and a clutch of the engine is placed in the second chamber communicating with the oil reservoir chamber.
10. The dry-sump lubrication type four-stroke cycle engine according to claim 9, wherein the clutch is placed in the second chamber so that the clutch is not immersed in oil.
11. The dry-sump lubrication type four-stroke cycle engine according to claim 1, wherein transmission gears of a transmission installed in the transmission chamber are disposed so that the transmission gears are not immersed in oil contained in the oil reservoir chamber, and an oil spraying unit is placed in the transmission chamber to spray oil on the transmission gears.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A nonvolatile semiconductor memory device comprising:
a memory cell array including two pages; and
a control circuit configured to read data stored in one page of the memory cell array and to rewrite part of the read data and write the rewritten data in the other page of the memory cell array,
wherein a part of the data in one page is different from a corresponding part of the data in the other page of the memory cell array.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array includes a plurality of memory blocks and each of said plurality of memory blocks includes a plurality of pages.
3. The nonvolatile semiconductor memory device according to claim 2, wherein one page of the memory cell array and the other page of the memory cell array are included in different memory blocks.
4. The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit includes a senselatch circuit that senses and latches the data stored in one page of the memory cell array.
5. The nonvolatile semiconductor memory device according to claim 4, wherein the senselatch circuit includes a plurality of latch circuits.
6. The nonvolatile semiconductor memory device according to claim 5, wherein said plurality of latch circuits are specified according to their addresses, and writing of the data is performed by the specified latch circuit.
7. The nonvolatile semiconductor memory device according to claim 6, wherein the control circuit includes a latch specifying circuit which specifies said plurality of latch circuits by the address.
8. The nonvolatile semiconductor memory device according to claim 7, wherein the latch specifying circuit is a column decoder circuit.
9. The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit includes a page specifying circuit which specifies the page in the memory cell array.
10. The nonvolatile semiconductor memory device according to claim 8, wherein the page specifying circuit is a row decoder circuit.
11. The nonvolatile semiconductor memory device according to claim 4, wherein the control circuit includes a data IO circuit connected to the senselatch circuit which outputs data latched by the senselatch circuit and which gives supplied data to be written to the senselatch circuit.
12. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array comprises a plurality of non-volatile transistors, said plurality of non-volatile transistors are serially connected to form a NAND cell.