1. A plasma display comprising:
a pair of substrates;
at least a pair of electrodes provided between the pair of substrates;
a phosphor layer provided between the pair of electrodes; and
an anti-reflection layer provided on an outer side of one substrate of the pair of substrates,
wherein the one substrate has a light-transmitting property,
wherein the anti-reflection layer comprises a plurality of pyramidal projections,
wherein each side of a base of one of the plurality of pyramidal projections is in contact with one side of a base of another pyramidal projection, and
wherein a space among the plurality of pyramidal projections is filled with a protective layer having a lower refractive index than a refractive index of the plurality of pyramidal projections.
2. A plasma display according to claim 1,
wherein apexes of the plurality of pyramidal projections are arranged at an equal distance.
3. A plasma display according to claim 1, wherein each of the plurality of pyramidal projections has a hexagonal pyramidal shape.
4. The plasma display according to claim 2, wherein a distance between the apexes of the plurality of pyramidal projections is 350 nm or less and a height of the plurality of pyramidal projections is 800 nm or higher.
5. The plasma display according to claim 3, wherein a filling factor of bases of the plurality of hexagonal pyramidal projections per unit area is 80% or more.
6. The plasma display according to claim 3,
wherein a first vertex of a hexagonal base of one of the plurality of hexagonal pyramidal projections is in contact with a first vertex of a hexagonal base of an adjacent hexagonal pyramidal projection, and
wherein a second vertex of the hexagonal base of the one of the plurality of hexagonal pyramidal projections is in contact with a second vertex of the hexagonal base of the adjacent hexagonal pyramidal projection.
7. A field emission display comprising:
a first substrate;
an electron-emission element over the first substrate;
a phosphor layer over the electron-emission element; and
an electrode over and in contact with the phosphor layer;
an anti-reflection layer provided over the second substrate,
wherein the second substrate has a light-transmitting property,
wherein the anti-reflection layer comprises a plurality of pyramidal projections,
wherein each side of a base of one of the plurality of pyramidal projections is in contact with one side of a base of another pyramidal projection, and
wherein a space among the plurality of pyramidal projections is filled with a protective layer having a lower refractive index than a refractive index of the plurality of pyramidal projections.
8. A field emission display according to claim 7,
wherein apexes of the plurality of pyramidal projections are arranged at an equal distance.
9. A field emission display according to claim 7, wherein each of the plurality of pyramidal projections has a hexagonal pyramidal shape.
10. The field emission display according to claim 8, wherein a distance between the apexes of the plurality of pyramidal projections is 350 nm or less and a height of the plurality of pyramidal projections is 800 nm or higher.
11. The field emission display according to claim 9, wherein a filling factor of bases of the plurality of hexagonal pyramidal projections per unit area is 80% or more.
12. The plasma display according to claim 9,
wherein a first vertex of a hexagonal base of one of the plurality of hexagonal pyramidal projections is in contact with a first vertex of a hexagonal base of an adjacent hexagonal pyramidal projection, and
wherein a second vertex of the hexagonal base of the one of the plurality of hexagonal pyramidal projections is in contact with a second vertex of the hexagonal base of the adjacent hexagonal pyramidal projection.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A commutating auto zero amplifier system, comprising:
a first amplifier;
a second amplifier;
a switching arrangement which defines a two phase operation, with the first amplifier in an output mode providing an output and the second amplifier in a zeroing mode during each phase;
a capacitor arrangement for storing offset voltages; and
a buffer amplifier for coupling the output from the first amplifier in the output mode to an input of the second amplifier in the zeroing mode.
2. A system as claimed in claim 1, wherein the first and second amplifiers each have first and second differential inputs.
3. A system as claimed in claim 2, wherein the first differential inputs are connected by the switching arrangement to main differential inputs to the system.
4. A system as claimed in claim 2, wherein the second differential inputs are connected to opposite ends of an offset storage capacitor network.
5. A system as claimed in claim 2, wherein when one of the first and second amplifiers is in the zeroing mode, a single one of the main differential inputs to the system is provided to both input terminals of the first differential input.
6. A system as claimed in claim 5, wherein when one of the first and second amplifiers is in the zeroing mode, one of the input terminals of the second differential input is coupled to the output of that amplifier, and the other is coupled to the output from the amplifier in the output mode by the buffer amplifier, and an offset voltage is stored in the capacitor arrangement.
7. A system as claimed in claim 1, wherein the capacitor arrangement comprises a first pair of series capacitors associated with the first amplifier, and a second pair of series capacitors associated with the second amplifier, and wherein the junctions between capacitors of the first pair and the second pair are connected together.
8. A system as claimed in claim 1, wherein the switching arrangement comprises a plurality of switches each of which has a gate signal controlled by one of two phase control signals.
9. A system as claimed in claim 1, implemented as a CMOS IC.
10. A method of operating a commutating auto zero amplifier system, comprising:
in a first phase, using a first amplifier to provide an output, using a buffer amplifier to couple the output from the first amplifier to the input of a second amplifier, and zeroing the second amplifier by storing offset voltages in a capacitor arrangement; and
in a second phase, using the second amplifier to provide an output, using the buffer amplifier to couple the output from the second amplifier to the input of the first amplifier, and zeroing the first amplifier by storing offset voltages in the capacitor arrangement.
11. A method as claimed in claim 10, wherein the first and second amplifiers each have first and second differential inputs.
12. A method as claimed in claim 11, wherein the first differential inputs are connected by the switching arrangement to main differential inputs to the system.
13. A method as claimed in claim 11, wherein the second differential inputs are connected to opposite ends of an offset storage capacitor network.
14. A method as claimed in claim 11, wherein when one of the first and second amplifiers is in the zeroing mode, a single one of main differential inputs to the system is provided to both input terminals of the first differential input.
15. A method as claimed in claim 14, wherein when one of the first and second amplifiers is in the zeroing mode, one of the input terminals of the second differential input is coupled to the output of that amplifier in zeroing mode, and the other one of the input terminals of the second differential input is coupled to the output from the amplifier in the output mode by the buffer amplifier, and an offset voltage is stored in the capacitor arrangement.
16. A method as claimed in claim 10, wherein controlling the system to switch between phases comprises controlling switches of a switching arrangement by one of two phase control signals.