1. A clock synthesizer for generating a desired clock signal from an input clock signal, comprising:
an exclusive OR gate, having a first input, a second input and an output, the first input coupled to receive a reset signal;
a delay string buffer having an input, a control input and an output, the delay string buffer input coupled to the output of the exclusive OR gate,
wherein;
a fine tuning unit, having an input, a control input and an output, the fine tuning unit input coupled to the output of the delay string buffer, the fine tuning unit output coupled to the second input of the exclusive OR gate; and
a control unit, having a first input, a second input and an output, the first input of the control unit coupled to receive the input clock signal and the second input of the control unit coupled to the output of the exclusive OR gate to generate a control signal at the output;
wherein the control input of the delay string buffer is coupled to receive the control signal to provide a coarse adjustment of the input clock signal corresponding to the desired clock signal, and wherein the control input of the fine tuning unit is coupled to receive the control signal to provide a fine adjustment of the input clock signal corresponding to the desired clock signal.
2. The clock synthesizer of claim 1, wherein the delay string buffer comprises:
a multiplexer, having a plurality of inputs, a control input and an output, the multiplexer control input coupled to receive the control signal, wherein the output of the multiplexer provides the output of the delay string buffer; and
a plurality of tristated buffers, each having an input, a tristate input, and output, each of the plurality of buffers coupled in series, the input of each of the plurality of buffers coupled to a respective input of the plurality of inputs of the multiplexer, the input of the least significant one of the plurality of tristated buffers coupled to receive the output of the exclusive OR gate through the input of the delay string buffer, each of the plurality of tristate inputs coupled to receive the control signal.
3. The clock synthesizer of claim 2, wherein the plurality of tristate inputs are coupled to receive the control signal to switch specific ones of the plurality of tristate inputs on and off to save power.
4. The clock synthesizer of claim 1, wherein the fine tuning unit comprises:
an input buffer coupled to the fine tuning unit input;
a plurality of AND gates, each having a first input, a second input and an output, each of the plurality of the first inputs of the AND gates coupled to the input buffer, each of the plurality of the second inputs of the AND gates coupled to receive a respective bit of the control signal;
a plurality of intermediate buffers coupled to a respective one of the plurality of outputs of the plurality of AND gates; and
an OR gate, having an output and a plurality of inputs corresponding to the number of plurality of AND gates, wherein the plurality of inputs couple to each respective one of the plurality of intermediate buffers.
5. The clock synthesizer of claim 4, wherein the plurality of intermediate buffers are tristate buffers, having an input, a tristate input and an output, each one of the plurality of the tristate inputs coupled to receive the control signal to switch specific ones of the plurality of tristate inputs on and off to save power.
6. The clock synthesizer of claim 1, wherein a bus width of the output of the control unit is equal to the sum of the number (N) of bits necessary to control the fine tuning unit and the number (M) of bits necessary to control the delay string buffer.
7. A method of synthesizing a multiplied clock signal at a desired frequency, comprising:
a. receiving an input clock signal in a clock synthesizer;
b. resetting initialization variables for a control unit within the clock synthesizer;
c. generating a coarse adjustment for a delay buffer string within the clock synthesizer;
d. setting the coarse adjustment by sending control signals from the control unit to the delay buffer string;
e. generating a fine adjustment for a fine tuning unit within the clock synthesizer;
f. setting the fine adjustment by sending control signals from the control unit to the fine tuning unit;
g. providing dither to a generated clock signal by shifting the signal modified by the fine tuning unit:
h. monitoring the frequency of the generated clock signal at predetermined intervals (R) of time per second;
i. returning to step (e) when a fine adjustment of the generated clock signal is necessary; and
j. returning to step (h) until the system that incorporates the clock synthesizer powers down.
8. The method of claim 7, wherein the method further comprises returning to step (c) when a coarse adjustment of the generated clock signal is necessary after the monitoring step (h).
9. The method of claim 7, wherein the step of generating a coarse adjustment, comprises:
a. counting the cycles of the output clock and the input clock;
b. calculating the ratio of output clock cycles to the number of input clock cycles;
c. comparing the ratio to a predetermined desired ratio corresponding to the desired frequency; and
d. calculating coarse adjustment for a delay buffer string within the clock synthesizer corresponding to the desired frequency based upon the comparison of ratios.
10. The method of claim 7, wherein the step of generating a fine adjustment, comprises:
a. counting the cycles of the output clock and the input clock;
b. calculating the ratio of output clock cycles to the number of input clock cycles;
c. comparing the ratio to a predetermined desired ratio corresponding to the desired frequency;
d. calculating a residue from the comparison of ratios; and
e. calculating fine adjustment for a fine tuning unit within the clock synthesizer corresponding to the desired frequency based upon the residue.
11. The method of claim 7, wherein predetermined number (R) is equal to 10.
12. The method of claim 7, wherein the method further comprises switching on and off a plurality of tristated buffers within the fine tuning unit to save power and generate a clock signal at the desired frequency.
13. The method of claim 7, wherein the method further comprises switching on and off a plurality of tristated buffers within the delay buffer string to save power and generate a clock signal at the desired frequency.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A module connection assembly, comprising:
a plurality of backplanes;
a plurality of sets of module connectors, each set of module connectors being capable of electrically connecting modules to a different one of the plurality of backplanes; and
configuration conductors providing rigid metallic conductor paths between module connectors on different backplanes;
the plurality of backplanes and the configuration conductors providing a plurality of links which electrically connect the plurality of sets of module connectors in a logical torus having multiple dimensions, each link including a cableless electrical signal path formed exclusively of rigid metallic material.
2. The module connection assembly of claim 1 wherein the configuration conductors provide:
a plurality of switches that are remotely controlled to electrically connect the plurality of sets of module connectors in the logical torus.
3. The module connection assembly of claim 1 wherein the logical torus is three dimensional.
4. The module connection assembly of claim 1 wherein each cableless electrical path in a particular dimension has substantially the same length.
5. The module connection assembly of claim 1 wherein each cableless electrical path in a particular dimension includes bit paths having substantially the same lengths.
6. The module connection assembly of claim 1 wherein each given backplane of the plurality of backplanes electrically connects one of the sets of module connectors in an interleaved manner.
7. The module connection assembly of claim 6 wherein the module connectors of the one set are disposed physically in row segments on the given backplane, and wherein the given backplane electrically connects the row segments in an interleaved manner.
8. The module connection assembly of claim 6 wherein the module connectors of the one set are disposed physically in row segments on the given backplane, and wherein the given backplane structure electrically connects the module connectors of the one set within each row segment in an interleaved manner.
9. The module connection assembly of claim 6 wherein the module connectors of the one set are disposed physically in row segments on the given backplane; wherein the row segments are disposed physically on the given backplane in a two dimensional array; and wherein the given backplane electrically connects the row segments in an interleaved manner and electrically connects the module connectors of the one set within each row segment in an interleaved manner such that the given backplane electrically connects the one of the sets of module connectors in an interleaved manner in three dimensions.