1. An information handling system comprising:
a processing system configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system;
a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system;
a chipset including a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system;
a first subgroup of power rails configured to be enabled during use of the processing system to power the shared resource and the non-shared resource of the processing system; and
a second subgroup of power rails configured to be enabled during use of the low-power processing system to power the shared resource of the processing system, and to further power a shared resource and a non-shared resource of the low-power processing system.
2. The information handling system of claim 1, further comprising a low-power processing module including a low power processor of the low-power processing system, wherein the low-power processing module is accessible to the chipset during operation of the processing system.
3. The information handling system of claim 1, further comprising:
wherein the chipset includes the low-power processing system;
wherein the power system is operable to enable the processing system separate from the low-power processing system; and
wherein the power system is further operable to enable the low-power processing system separate from the processing system.
4. The information handling system of claim 1, further comprising:
a low-power processing module externally coupled to the chipset;
a video processing resource within the chipset and accessible to the processing system during operation of the processing system;
wherein the video processing resource is accessible to the low-power processing module during operation of the low-power processing system and a reduced operating state of the processing system;
a power subsystem of the power system configured to enable a portion of the chipset; and
wherein the low-power processing system is configured to access the enabled portion of the chipset to output video using the shared resource of the processing system during the reduced operating state of the processing system.
5. The information handling system of claim 1, further comprising:
a video input source operably coupled to the chipset during operation of the low-power processing system;
a video output resource of the processing system configured to identify the video input source; and
wherein the video output resource is configured to process a video input from the video input source to a display format of the display.
6. The information handling system of claim 1, wherein the power system is further configured to enable a power rail of the first group of power rails and a power rail of a the second group of power rails based on an operating state of the processing system and operating state of the low-power processing system.
7. The information handling system of claim 1, further comprising:
wherein the chipset includes a low power processor of the low-power processing system; and
a peripheral switching module integrated within the chipset and configured to couple an output of the chipset to the shared resource during use of the processor and the low power processor.
8. The information handling system of claim 3, further comprising:
a video processing resource within the chipset and accessible to the processing system during operation of the processing system; and
wherein the video processing resource is accessible to the low-power processing system during operation of the low-power processing system.
9. The information handling system of claim 8, wherein the video processing resource includes:
a video raster coupled to the chipset and operable to be accessed as a shared video output resource; and
wherein the video raster is further accessible to the low-power processing system and the processing system to simultaneously output video of the low-power processing system and video of the processing system to a shared video display resource.
10. The information handling system of claim 5, further comprising a power subsystem configured to enable the video output resource.
11. A chipset comprising:
a processor configured to access a shared resource of a processing system during operation of the processing system;
a power system configured to enable a powering of the shared resource during operation of the processing system and operation of a low-power processing system;
a low power processor of the low-power processing system, wherein the low power processor is configured to be enabled during a reduced operation of the processor; and
a low power processor subsystem power source configured to be enabled in response to enabling the low power processor separate from the processing system.
12. The chipset of claim 11, further comprising a peripheral switching module configured to couple an output to the shared resource during use of processing system and the low-power processing system.
13. The chipset of claim 11, wherein the processor is a part of the processing system.
14. The chipset of claim 11, further comprising a low power processor of the low-power processing system.
15. The chipset of claim 12, wherein the shared resource includes:
a video display accessible to the low-power processing system during operation of the low-power processing system; and
wherein the video display is accessible to the processing system during operation of the processing system.
16. The chipset of claim 11, further comprising:
a low power processor of the low-power processing system; and
wherein the processor is a part of the processing system.
17. An information handling system comprising:
a processing system configured to access a shared resource and a non-shared resource during operation of the processing system;
a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from operation of the processing system;
a power system configured to power the processing system, the low-power processing system, the shared resource, and the non-shared resource; and
a chipset comprising:
a processor configured to access the shared resource of the processing system during the operation of the processing system;
a low power processor configured to access the shared resource of the processing system during the operation of the low-power processing system; and
a low power processor subsystem power source configured to be enabled in response to enabling the low power processor separate from the processing system.
18. The information handling system of claim 17, further comprising:
a control module operably coupled to the chipset and the power system to initiate powering the shared resource and the non-shared resource; and
a peripheral switching module integrated within the chipset and configured to couple an output of the chipset to the shared resource during use of processing system and the low-power processing system.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
the memory cell array is divided into a plurality of sub-arrays by boundaries which are perpendicular to the extending directions of the memory lines;
a wire channel in each of the sub-arrays is shifted from a wire channel in an adjacent sub-array in the directions of the boundaries;
an array boundary wire channel is provided along the boundaries between the adjacent sub-arrays; and
the signal line extends through a wire channel in each of the sub-arrays and the array boundary wire channel.
2. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
the plurality of dummy wire patterns have a two-layer structure including a plurality of lower-layer dummy wire patterns and a plurality of upper-layer dummy wire patterns;
the plurality of lower-layer dummy wire patterns are provided such that each lower-layer dummy wire pattern covers at least one of the bit lines, and a wire channel is formed between the lower-layer dummy wire patterns so as to extend in the direction of the bit lines; and
the plurality of upper-layer dummy wire patterns are provided such that each upper-layer dummy wire pattern covers at least one of the word lines, and a wire channel is formed between the upper-layer dummy wire patterns so as to extend in the direction of the word lines.
3. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
the plurality of dummy wire patterns have a two-layer structure including a plurality of lower-layer dummy wire patterns and a plurality of upper-layer dummy wire patterns;
the plurality of lower-layer dummy wire patterns are provided such that each lower-layer dummy wire pattern covers at least one of the word lines, and a wire channel is formed between the lower-layer dummy wire patterns so as to extend in the direction of the word lines; and
the plurality of upper-layer dummy wire patterns are provided such that each upper-layer dummy wire pattern covers at least one of the bit lines, and a wire channel is formed between the upper-layer dummy wire patterns so as to extend in the direction of the bit lines.
4. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
first and second memory cell arrays are provided on the same chip, each of the first and second memory cell arrays including a plurality of word lines and a plurality of bit lines, the bit lines crossing the word lines at right angles;
a series of lower-layer wire channels are formed between a plurality of lower-layer dummy wire patterns, the lower-layer wire channels extending in the bit line direction on the first memory cell array, the lower-layer wire channels extending in the word line direction on the second memory cell array;
a series of upper-layer wire channels are formed between a plurality of upper-layer dummy wire patterns, the upper-layer wire channels on the first memory cell array extending in the word line direction, the upper-layer wire channels on the second memory cell array extending in the word line direction; and
the signal line extends over the first and second memory cell arrays through the lower-layer wire channels or the upper-layer wire channels.
5. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of dummy wire patterns formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the dummy wire patterns, wherein:
the plurality of dummy wire patterns have a two-layer structure including a plurality of lower-layer dummy wire patterns and a plurality of upper-layer dummy wire patterns;
the plurality of lower-layer dummy wire patterns are provided such that each lower-layer dummy wire pattern covers four or more of a plurality of intersection points of the word lines and the bit lines, and a wire channel is formed between the lower-layer dummy wire patterns to have a lattice shape; and
the plurality of upper-layer dummy wire patterns are provided such that each upper-layer dummy wire pattern covers four or more of a plurality of intersection points of the word lines and the bit lines in a combination different from that of the lower-layer dummy wire patterns, and a wire channel having a lattice shape is formed between the upper-layer dummy wire patterns.
6. A semiconductor device, comprising:
a memory cell array including a plurality of memory lines, the memory lines including a plurality of word lines or a plurality of bit lines, the bit lines crossing the word lines at right angles;
a plurality of wiring-prohibited regions formed on the memory cell array to cover at least part of the memory lines; and
a signal line extending over the memory cell array through a wire channel formed between the wiring-prohibited regions, wherein:
the signal line is a metal line formed in the same layer which includes the wiring-prohibited regions and a route; and
a route of the signal line is determined using an automatic wiring tool.