1. A method of providing normalization of time of local clock circuits of two or more spatially-located receivers of respective monitoring stations, said method comprising:
transmitting at least two RF pulses to define a time reference interval;
detecting said RF pulses at said receivers;
at respective monitoring associated with said receivers, measuring durations of said time reference interval according to said detecting step;
determining a relationship between durations measured at said monitoring stations; and
providing normalization of time of said local clock circuits at two or more monitoring stations according to said relationship.
2. The method of claim 1, wherein said transmitting step further includes transmitting at least two UWB pulses that each comprise a signal burst of a few cycles of RF energy.
3. The method of claim 2, wherein:
said measuring step includes counting unit increments of time to measure said time reference interval between said UWB pulses and latching a clock count to measure said durations; and
said processing step includes normalizing time-of-arrival measurements among receivers of said monitoring stations by controlling the frequency of at least one local clock circuit of a monitoring station to maintain the relationship fixed with respect to a frequency of a local clock of a selected master monitoring station.
4. The method of claim 3, further comprising:
wirelessly receiving at a central processing hub digital information representing clock count information and time-of-arrival measurements of an object tag transmission; and
normalizing said time-of-arrival measurements according to said relationship.
5. The method of claim 2, further comprising providing a ring counter to measure said time reference interval between said UWB pulses and latching a clock count to measure said durations.
6. A method of normalizing independent clocks of respective receivers of remote monitoring stations, said method comprising:
transmitting an ultra wideband (UWB) pulse pair,
determining at first and second monitoring stations a respective clock count indicative of a locally measured time interval between said pulse pair, each said clock count being derived by incremental measurement of time units,
determining a ratio between clock counts of said first and second monitoring stations using programmed processor module, and
utilizing said ratio as a reference to normalize time of local clocks that generate each said clock count.
7. The method of claim 6, wherein said utilizing step includes normalizing time by synchronizing local clocks that generate each said clock count.
8. The method of claim 6, wherein said utilizing step includes normalizing time by applying a correction to time-of-arrival measurements taken at respective monitoring stations.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory with semiconductor memory cells, comprising:
a substrate, the substrate having a substrate surface;
a first trench, the first trench being arranged in the substrate and having a lower region, a central region and an upper region, the first trench having a trench capacitor formed therein;
a first direction and a second direction, the second direction crossing the first direction;
a second trench, the second trench being arranged beside the first trench with respect to the first direction in the substrate, the second trench having a trench capacitor formed therein;
a first longitudinal trench and a second longitudinal trench, the first and second longitudinal trenches being relatively arranged parallel to one another and extend along the first direction, the first longitudinal trench adjoining the first trench and the second trench, the second longitudinal trench adjoining the first trench and the second trench on the opposite side of the first trench and the second trench with respect to the first longitudinal trench;
an active region, the active region being arranged between the first longitudinal trench, the second longitudinal trench, the first trench and the second trench;
a first spacer word line, the first spacer word line being arranged in the first longitudinal trench laterally at the active region;
a second spacer word line, the second spacer word line being arranged in the second longitudinal trench laterally at the active region;
conductive connecting webs, the webs being arranged in the upper region of the first trench or of the second trench as connections between the first spacer word line and the second spacer word line; and
a vertical selection transistor, which has a source doping region, a drain doping region and a channel, the channel being arranged between the source doping region and the drain doping region in the active region and the source doping region being connected to the trench capacitor and the drain doping region being connected to a bit line, the bit line being arranged on the substrate and crossing the first spacer word line wherein the thickness of the connecting webs in the direction of the first spacer word line is less than half the width of the first trench in the direction of the first spacer word line.
2. The semiconductor memory according to claim 1, wherein a first connecting web and a second connecting web are arranged in the first trench, the first connecting web adjoining the active region and the second connecting web being arranged at a sidewall of the first trench opposite to the first connecting web in the upper region of the first trench.
3. The semiconductor memory according to claim 1, wherein the active region is enclosed by gate electrodes formed by the spacer word line and the connecting web.
4. The semiconductor memory according to claim 2, wherein a connecting web is, in each case, arranged between two active regions.
5. The semiconductor memory according to claim 2, wherein the second connecting web, proceeding from the substrate surface, extends relatively more deeply into the first trench than the first connecting web.
6. The semiconductor memory according to claim 1, wherein an insulation collar is arranged on the side wall of the trench in the central region of the trench.
7. The semiconductor memory according to claim 1, wherein a conductive trench filling is arranged as an inner capacitor electrode of the trench capacitor in the lower region and the central region of the trench.
8. The semiconductor memory according to claim 7, wherein an insulating layer is arranged on the conductive trench filling, the insulating layer extending from the first connecting web to the second connecting web, the insulating layer having an angled course at the second connecting web so that the insulating layer covers the second connecting web along a relatively longer distance than the first connecting web.
9. The semiconductor memory according to claim 1, wherein the insulation collar, along the periphery of the first trench, has a relatively uniform distance from the substrate surface.
10. The semiconductor memory according to claim 3, wherein a connecting web is, in each case, arranged between two active regions.