1. A method comprising:
composing, by a data processor, first uplink pilot signals and a second uplink pilot signal;
transmitting, by at least one transmitter, the first uplink pilot signals during sub-bands and slots of a time-frequency resource space, wherein at least three first portions of the time-frequency resource space (a first long block 1 (LB1), a first long block 2 (LB2) and a first long block 3 (LB3)) are reserved for the first uplink pilot signals, wherein the first LB1 and the first LB2 comprise in-band pilot signals transmitted using a dedicated pilot code; and
transmitting, by the at least one transmitter, the second uplink pilot signal during a second portion of the time-frequency resource space (a second long block 3 (LB3)) using a frequency hopping pattern and a pilot code allocation that are based on a slot and a sub-band in which the first LB3 is transmitted.
2. The method of claim 1, wherein the frequency hopping pattern for the second LB3 is based on parameters comprising: L=length of the hopping pattern and y=hopping pattern index (1 . . . L), wherein z=slot index (1 . . . L), and wherein the hopping pattern (z)=rem(z\u22121+(y\u22121),L)+1.
3. The method of claim 1, wherein the frequency hopping pattern (X) for the second LB3 meets the following criterion:
X(R)=B,
where
B=first active sub-band; and
R=first active slot.
4. The method of claim 1, wherein the dedicated pilot code comprises a code in a code list.
5. The method of claim 4, wherein codes in the code list comprise cyclic shifts of a constant amplitude zero autocorrelation (CAZAC) code.
6. The method of claim 1, wherein the uplink comprises a universal terrestrial radio access network-long term evolution (UTRAN-LTE) uplink, and wherein a channel quality indication rate for at least the second uplink pilot signal is constrained.
7. A tangible computer-readable medium that stores program instructions, execution of the program instructions by a processor resulting in operations comprising:
composing first uplink pilot signals and a second uplink pilot signal;
transmitting the first uplink pilot signals during sub-bands and slots of a time-frequency resource space, wherein at least three first portions of the time-frequency resource space (a first long block 1 (LB1), a first long block 2 (LB2) and a first long block 3 (LB3)) are reserved for the first uplink pilot signals, wherein the first LB1 and the first LB2 comprise in-band pilot signals transmitted using a dedicated pilot code; and
transmitting the second uplink pilot signal during a second portion of the time-frequency resource space (a second long block 3 (LB3)) using a frequency hopping pattern and a pilot code allocation that are based on a slot and a sub-band in which the first LB3 is transmitted.
8. The computer-readable medium of claim 7, wherein the frequency hopping pattern for the second LB3 is based on parameters comprising: L=length of the hopping pattern and y=hopping pattern index (1 . . . L), wherein z=slot index (1 . . . L), and wherein the hopping pattern (z)=rem(z\u22121+(y\u22121),L)+1.
9. The computer-readable medium of claim 7, wherein the frequency hopping pattern (X) for the second LB3 meets the following criterion:
X(R)=B,
where
B=first active sub-band; and
R=first active slot.
10. The computer-readable medium of claim 7, wherein the dedicated pilot code comprises a code in a code list.
11. The computer-readable medium of claim 10, wherein codes in the code list comprise cyclic shifts of a constant amplitude zero autocorrelation (CAZAC) code.
12. The computer-readable medium of claim 7, wherein the uplink comprises a universal terrestrial radio access network-long term evolution (UTRAN-LTE) uplink, and wherein a channel quality indication rate for at least the second uplink pilot signal is constrained.
13. An apparatus comprising:
a data processor configured to compose first uplink pilot signals and a second uplink pilot signal; and
a transmitter configured to transmit the first uplink pilot signals during sub-bands and slots of a time-frequency resource space, wherein at least three portions of the time-frequency resource space (a first long block 1 (LB1), a first long block 2 (LB2) and a first long block 3 (LB3)) are reserved for the first uplink pilot signals, wherein the first LB1 and the first LB2 comprise in-band pilot signals transmitted using a dedicated pilot code, wherein the transmitter is further configured to transmit a the second uplink pilot signal during a second portion of the time-frequency resource space (a second long block 3 (LB3)) using a frequency hopping pattern and a pilot code allocation that are based on a slot and a sub-band in which the first LB3 is transmitted.
14. The apparatus of claim 13, wherein the frequency hopping pattern for the second LB3 is based on parameters comprising: L=length of the hopping pattern and y=hopping pattern index (1 . . . L), wherein z=slot index (1 . . . L), and wherein the hopping pattern (z)=rem(z\u22121+(y\u22121),L)+1.
15. The apparatus of claim 13, wherein the frequency hopping pattern (X) for the second LB3 meets the following criterion:
X(R)=B,
where
B=first active sub-band; and
R=first active slot.
16. The apparatus of claim 13, wherein the dedicated pilot code comprises a code in a code list.
17. The apparatus of claim 16, wherein codes in the code list comprise cyclic shifts of a constant amplitude zero autocorrelation (CAZAC) code.
18. The apparatus of claim 13, wherein the uplink comprises a universal terrestrial radio access network-long term evolution (UTRAN-LTE) uplink, and wherein a channel quality indication rate for at least the second uplink pilot signal is constrained.
19. The apparatus of claim 13, wherein the apparatus comprises a mobile phone.
20. The apparatus of claim 13, embodied at least partially in an integrated circuit.
21. An apparatus comprising:
processing means for composing first uplink pilot signals and a second uplink pilot signal; and
transmitting means for transmitting the first uplink pilot signals during sub-bands and slots of a time-frequency resource space, wherein at least three portions of the time-frequency resource space (a first long block 1 (LB1), a first long block 2 (LB2) and a first long block 3 (LB3)) are reserved for the first uplink pilot signals, wherein the first LB1 and the first LB2 comprise in-band pilot signals transmitted using a dedicated pilot code, wherein the transmitting means is further for transmitting the second uplink pilot signal during a second portion of the time-frequency resource space (a second long block 3 (LB3)) using a frequency hopping pattern and a pilot code allocation that are based on a slot and a sub-band in which the first LB3 is transmitted.
22. The apparatus of claim 21, wherein the processing means comprises a data processor and the transmitting means comprises at least one transmitter or at least one transceiver.
23. The apparatus of claim 21, wherein the frequency hopping pattern for the second LB3 is based on parameters comprising: L=length of the hopping pattern and y=hopping pattern index (1 . . . L), wherein z=slot index (1 . . . L), and wherein the hopping pattern (z)=rem(z\u22121+(y\u22121),L)+1.
24. The apparatus of claim 21, wherein the frequency hopping pattern (X) for the second LB3 meets the following criterion:
X(R)=B,
where
B=first active sub-band; and
R=first active slot.
25. The apparatus of claim 21, wherein the dedicated pilot code comprises a code in a code list, wherein codes in the code list comprise cyclic shifts of a constant amplitude zero autocorrelation (CAZAC) code.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of designing a circuit, comprising:
annotating relative positions of instantiated hierarchical macro cells within a standard cell design;
converting said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit; and
routing said grid assigned circuit to form a routed circuit;
wherein annotating includes annotating relative pin positions within said standard cell design;
wherein annotating includes altering a relative position of a pin to facilitate dense signal line routine within said standard cell design; and
wherein annotating said relative pin position includes specifying a pin perimeter position, a pin column, a pin track, and a pin metal layer for a pin.
2. The method of claim 1 wherein annotating relative positions of instantiated hierarchical macro cells includes altering a relative position of an instantiated hierarchical macro cell to form a more compact standard cell configuration.
3. The method of claim 2 wherein altering a relative position of an instantiated hierarchical macro cell alters positions of standard cells associated with said instantiated hierarchical macro cell.
4. A method of designing a circuit, comprising:
annotating relative positions of instantiated hierarchical macro cells within a standard cell design;
converting said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit; and
routing said grid assigned circuit to form a routed circuit;
wherein annotating relative positions of instantiated hierarchical macro cells includes annotating individual standard cells contained within said instantiated hierarchical macro cells; and
wherein annotating said relative positions of said instantiated hierarchical macro cells includes specifying a row offset, a column offset, and a stack offset for each individual standard cell contained within said instantiated hierarchical macro cells.
5. The method of claim 4 wherein annotating includes annotating relative pin positions within said standard cell design.
6. The method of claim 5 wherein annotating includes altering a relative position of a pin to facilitate dense signal line routing within said standard cell design.
7. A method of designing a circuit, comprising:
annotating relative positions of instantiated hierarchical macro cells within a standard cell design;
converting said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit; and
routing said grid assigned circuit to form a routed circuit;
wherein said converting includes forming a grid assigned circuit specifying bit slice datapaths.
8. The method of claim 7 wherein said converting includes specifying a bit slice datapath including multiple standard cell instances, each standard cell instance being positionally defined by a column position, a row position, and a stack position.
9. The method of claim 7 further comprising verifying the performance of said routed circuit.
10. The method of claim 9 further comprising selectively repeating said annotating, converting, and placing and routing in response to said verifying.
11. The method of claim 7 wherein said converting forms a grid assigned circuit that is a placed circuit.
12. A computer system, comprising:
a standard cell layout generation tool to produce an initial design of standard cells;
a relative position annotation module to facilitate the annotation of relative positions of instantiated hierarchical macro cells and pins within said initial design; and
an absolute position assignment module to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit;
wherein said relative position annotation module facilitates the alteration of a relative position of an instantiated hierarchical macro cell to form a more compact standard cell configuration;
wherein said relative position annotation module facilitates the annotation of individual standard cell cells by row offset, column offset, and stack offset.
13. The computer system of claim 12 further comprising:
a circuit verifier to verify performance of a routed circuit derived from said grid assigned circuit.
14. The computer system of claim 13 further comprising a criteria verification module to invoke said relative position annotation module when specified circuit performance is not met.
15. The computer system of claim 12 wherein said relative position annotation module facilitates the alteration of a pin position to facilitate dense signal line routing within said standard cells.
16. A computer system, comprising:
a standard cell layout generation tool to produce an initial design of standard cells;
a relative position annotation module to facilitate the annotation of relative positions of instantiated hierarchical macro cells and pins within said initial design, wherein said relative position annotation module facilitates the annotation of a pin by pin perimeter position, pin column, pin track, and pin metal layer; and
an absolute position assignment module to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit.
17. The computer system of claim 16 wherein said relative position annotation module tracks the relative positions of individual standard cells contained within said instantiated hierarchical macro cells.
18. A computer system, comprising:
a standard cell layout generation tool to produce an initial design of standard cells;
a relative position annotation module to facilitate the annotation of relative positions of instantiated hierarchical macro cells and pins within said initial design;
an absolute position assignment module to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit, wherein said absolute position assignment module forms a grid assigned placed circuit specifying routed bit slice datapaths.
19. The computer system of claim 18 wherein said absolute position assignment module forms a bit slice datapath including multiple standard cell instances, each standard cell instance being positionally defined by a column position, a row position, and a stack position.
20. A computer readable medium to direct a computer to function in a specified manner, comprising:
first instructions to annotate relative positions of instantiated hierarchical macro cells within a standard cell design, wherein said first instructions include instructions to facilitate the annotation of relative pin positions within said standard cell design;
second instructions to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit; and
third instructions to route said grid assigned circuit to form a routed circuit.
21. The computer readable medium of claim 20 wherein said first instructions include instructions to facilitate the altering of a relative position of an instantiated hierarchical macro cell to form a more compact standard cell design.
22. A computer readable medium to direct a computer to function in a specified manner, comprising:
first instructions to annotate relative positions of instantiated hierarchical macro cells within a standard cell design, wherein said first instructions include instructions to facilitate the specification of a pin perimeter position, a pin column, a pin track, and a pin metal layer for a pin;
second instructions to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit; and
third instructions to route said grid assigned circuit to form a routed circuit.
23. The computer readable medium of claim 22 wherein said first instructions include instructions to track the relative positions of individual standard cells contained within said instantiated hierarchical macro cells.
24. A computer readable medium to direct a computer to function in a specified manner, comprising:
first instructions to annotate relative positions of instantiated hierarchical macro cells within a standard cell design, wherein said first instructions include instructions to track the relative positions of individual standard cells contained within said instantiated hierarchical macro cells, and wherein said first instructions include instructions to facilitate the specification of a row offset, a column offset, and a stack offset for individual standard cells contained within said instantiated hierarchical macro cells;
second instructions to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit; and
third instructions to route said grid assigned circuit to form a routed circuit.
25. A computer readable medium to direct a computer to function in a specified manner, comprising:
first instructions to annotate relative positions of instantiated hierarchical macro cells within a standard cell design;
second instructions to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit, wherein said second instructions include instructions to form a grid assigned placed circuit specifying bit slice datapaths; and
third instructions to route said grid assigned circuit to form a routed circuit.
26. The computer readable medium of claim 25 wherein said first instructions include instructions to facilitate the altering of a relative position of a pin to facilitate dense signal line routing within said standard cell design.
27. A computer readable medium to direct a computer to function in a specified manner, comprising:
first instructions to annotate relative positions of instantiated hierarchical macro cells within a standard cell design;
second instructions to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit, wherein said second instructions include instructions to form a grid assigned placed circuit specifying bit slice datapaths, and wherein said second instructions include instructions to form a bit slice datapath including multiple standard cell instances, each standard cell instance being positionally defined by a column position, a row position, and a stack position; and
third instructions to route said grid assigned circuit to form a routed circuit.
28. The computer readable medium of claim 27 further comprising fourth instructions to verify the performance of said routed circuit.
29. A computer readable medium to direct a computer to function in a specified manner, comprising:
first instructions to annotate relative positions of instantiated hierarchical macro cells within a standard cell design;
second instructions to convert said relative positions of said instantiated hierarchical macro cells to absolute grid position locations to form a grid assigned circuit; and
third instructions to route said grid assigned circuit to form a routed circuit;
fourth instructions to verify the performance of said routed circuit; and
fifth instructions to invoke the operation of said first instructions, said second instructions, and said third instructions when specified circuit performance is not met.