1. An anhydrous cosmetic composition comprising:
(A) an anhydrous mixture of:
i. an aminosilicone with the structure:
wherein X is selected from the group consisting of CH3, OCH3, R, or a combination thereof; wherein R is NHCH2CH2NH2 selected from the group consisting of R\u2032NH2 and R\u2032NHR\u2033NH2; wherein R\u2032 and R\u2033 are selected from the group consisting of ethylene, propylene, isobutylene, isopropylene, alkylene, and cycloalkylene alkylene ether; wherein m is 1 to 5; wherein n is 10 to 100; and wherein z is 8 to 450; and
ii. an organosiloxane resin; and
(B) a volatile carrier.
2. The cosmetic composition of claim 1 further comprising the group consisting of thickeners and structure builders.
3. The cosmetic composition of claim 2 wherein the thickeners and structure builders are selected from the group consisting of organically modified clays, fumed silica, silgels, alkyl silicone waxes, silicone polyamide, diblocktriblock copolymers and silsequioxane crosspolymers.
4. The cosmetic composition of claim 3 wherein the organically modified clay is selected from the group consisting of hectorite, bentonite, smectite, montmorillonite clay and mixtures thereof.
5. The cosmetic composition of claim 1 wherein the organosiloxane resin comprises R3SiO12 \u201cM\u201d units, R2SiO \u201cD\u201d units, RSiO32 \u201cT\u201d units, SiO2 \u201cQ\u201d units and mixtures thereof in a ratio selected to satisfy the relationship RnSiO(4-n)2, wherein n is from about 1.0 to about 1.50 and R is a methyl group.
6. The cosmetic composition of claim 1 wherein the organosiloxane resin comprises R3SiO12 \u201cM\u201d units and SiO2 \u201cQ\u201d units wherein the ratio of R3SiO12 to SiO2 is about 0.6 to about 2.0.
7. The cosmetic composition of claim 1 further comprising a diorganopolysiloxane polymer.
8. The cosmetic composition of claim 7 wherein the diorganopolysiloxane polymer comprises repeating units of the formula (R2SiO), where R is a hydrocarbon side group containing from 1 to 6 carbon atoms.
9. The cosmetic composition of claim 8 wherein said hydrocarbon side group is selected from the group consisting of methyl, ethyl, propyl, isopropyl, butyl, isobutyl, t-butyl, amyl, hexyl, vinyl, allyl, cyclohexyl, phenyl, fluoroalkyl and mixtures thereof.
10. The cosmetic composition of claim 8 wherein the diorganopolysiloxane polymer is terminated by triorganosilyl groups of the formula (R\u20323Si) where R\u2032 is a monovalent hydrocarbon radical selected from the group consisting of 1 to 6 carbon atoms, hydroxyl groups, an alkoxyl groups and mixtures thereof.
11. The cosmetic composition of claim 10 wherein the diorganopolysiloxane polymer is a polydimethyl siloxane.
12. The cosmetic composition of claim 1 wherein the modified silicone has a viscosity of from about 100 cSt to about 2,000,000 cSt at 25\xb0 C.
13. The cosmetic composition of claim 7 wherein the diorganopolysiloxane polymer has a viscosity of from at least about 1,000,000 cSt at 25\xb0 C.
14. The cosmetic composition of claim 1 wherein the volatile carrier is selected from the group consisting of hydrocarbon oils, silicone oils and mixtures thereof.
15. The cosmetic composition of claim 1 wherein the volatile carrier is isododecane.
16. A lip product comprising the composition of claim 1 having a viscosity of from about 500 cP to about 15,000 cP.
17. The cosmetic composition of claim 1 wherein the composition is paired with a topcoat product comprising a safe and effective amount of modified silicones selected from the group consisting of aminosilicones, carboxy modified silicones, epoxy modified silicones, and mixtures thereof.
18. The cosmetic composition of claim 1 wherein the composition is paired with a topcoat product comprising a safe and effective amount of a polymeric vegetable oil emollient.
19. The cosmetic composition of claim 1 wherein the composition is paired with a topcoat product comprising a safe and effective amount of a silicone modified fluorinated polymer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system comprising:
at least one first input component for receiving a first transport stream from an external source;
at least one second input component for receiving a second transport stream from a memory; and
at least one multiplexer for connecting the at least one first input component and the at least one second input component to an interface which is arranged to provide an output stream to a decoder; wherein the at least one second input component comprises:
a configuration register comprising a software configuration value used to indicate to the interface that a predetermined amount of data is available to be output from a buffer in a software writable transport stream register, and
the software writable transport stream register comprising a pace counter that controls a stream data rate of transfer of the second transport stream from the memory to the interface so that the transport stream is re-playable via at least fast forward and rewind, wherein:
when the pace counter matches the software configuration value, a valid signal is asserted for one system clock cycle and provided to the interface,
the valid signal indicates that at least one byte read from the buffer is valid, and
the amount of cycles between each valid byte output by the at least one second input component is programmed in the pace counter.
2. The system as claimed in claim 1, wherein said at least one second input component from memory comprises a transport stream.
3. The system as claimed in claim 1, wherein, when a predetermined amount of space in the buffer is available, a software request flag is asserted.
4. The system as claimed in claim 1, wherein said buffer comprises a first-in-first out (FIFO) buffer.
5. The system as claimed in claim 1, wherein half the size of the buffer equals a bit rate of the data input to the at least one second input component multiplied by a time it takes to read the data from the memory and write the data to the at least one second input component.
6. The system as claimed in claim 1, wherein the software writable transport stream register is provided in said at least one second input component to convert a serial stream of data into a parallel stream of data.
7. The system as claimed in claim 1, wherein said memory is external to said system.
8. The system as claimed in claim 1, wherein said memory is in said system.
9. The system as claimed in claim 1, wherein said memory comprises at least one of CD-ROM, hard disk, floppy disk, CPU, and RAM.
10. The system as claimed in claim 1, wherein said at least one first input component is arranged to receive a transport stream from a cable or satellite link.
11. The system as claimed in claim 1, wherein said at least one second input component comprises a clock, said clock providing a clock signal for controlling the output of data to said at least one second input component.
12. The system as claimed in claim 1, wherein said at least one second input component is arranged to output valid data only.
13. The system of claim 1, wherein the at least one second input component provides an output to the interface in such a form that the interface is not able to determine if the output comes from the external source or from the memory.
14. An integrated circuit comprising:
at least one first input component for receiving a first transport stream from an external source;
at least one second input component for receiving a second transport stream from a memory; and
at least one multiplexer for connecting the at least one first input component and the at least one second input component to an interface which is arranged to provide an output stream to a decoder; wherein the at least one second input component comprises:
a configuration register comprising a software configuration value used to indicate to the interface that a predetermined amount of data is available to be output from a buffer in a software writable transport stream register, and
the software writable transport stream register comprising a pace counter that controls a stream data rate of transfer of the second transport stream from the memory to the interface so that the transport stream is re-playable via at least fast forward and rewind, wherein:
when the pace counter matches the software configuration value, a valid signal is asserted for one system clock cycle and provided to the interface,
the valid signal indicates that at least one byte read from the buffer is valid, and
the amount of cycles between each valid byte output by the at least one second input component is programmed in the pace counter.
15. The integrated circuit of claim 14, wherein the at least one second input component provides an output to the interface in such a form that the interface is not able to determine if the output comes from the external source or from the memory.
16. A set top box comprising:
at least one first input component for receiving a broadcast transport stream from an external source;
at least one second input component for receiving a transport stream from a memory; and
at least one multiplexer for connecting the at least one first input component and the at least one second input component to an interface which is arranged to provide an output stream to a decoder; wherein at least one the second input component comprises:
a configuration register comprising a software configuration value used to indicate to the interface that a predetermined amount of data is available to be output from a buffer in a software writable transport stream register, and
the software writable transport stream register comprising a pace counter that controls a stream data rate of transfer of the transport stream from the memory to the interface so that the transport stream is re-playable via at least fast forward and rewind, wherein:
when the pace counter matches the software configuration value, a valid signal is asserted for one system clock cycle and provided to the interface,
the valid signal indicates that at least one byte read from the buffer is valid, and
the amount of cycles between each valid byte output by the at least one second input component is programmed in the pace counter.
17. The set top box of claim 16, wherein the at least one second input component provides an output to the interface in such a form that the interface is not able to determine if the output comes from the external source or from the memory.