1. A memory system, comprising:
a memory having a rewritable data storage portion; and
a controller for managing data stored in the memory and controlling the transfer of data between the memory system and a host to which it is connected, where the controller can operate the memory system according to a plurality of modes, each of the modes having a different level of performance for operations involving the writing of data, including a second mode of higher performance than a first mode, wherein the controller operates the memory normally according to the first of the modes and, in response to the controller determining a system related high latency situation, the controller instead operates the memory according to the second of the modes.
2. The memory system of claim 1, wherein said high latency situation is an error during programming.
3. The memory system of claim 1, wherein said high latency situation is an error during a data relocation operation.
4. The memory system of claim 1, wherein said high latency situation is a garbage collection operation.
5. The memory system of claim 1, wherein the second of the modes uses a lower level of error detection and correction than the first of the modes.
6. The memory system of claim 1, wherein the second of the modes uses a faster programming sequence than the first of the modes.
7. The memory system of claim 6, wherein the second of the modes uses a faster clock speed than the first of the modes.
8. The memory system of claim 7, wherein the second of the modes uses programming pulses of longer duration than the first of the modes.
9. The memory system of claim 7, wherein the second of the modes uses programming pulses of greater amplitude than the first of the modes.
10. The memory system of claim 1, wherein the controller additionally operates the memory according to a third of the modes in response to an additional system related situation, wherein the third of the modes is of greater reliability than the first of the modes.
11. The memory system of claim 10, wherein the additional system related situation is partial page programming.
12. The memory system of claim 10, wherein the additional system related situation is a low voltage condition.
13. The memory system of claim 10, wherein the third of the modes utilizes a higher degree of error detection and correction than the first of the modes.
14. The memory system of claim 10, wherein the third of the modes utilizes a slower programming sequence than the first of the modes.
15. The memory system of claim 10, wherein the third of the modes utilizes a slower clock rate than the first of the modes.
16. The memory system of claim 10, wherein the third of the modes utilizes programming pulses of shorter duration than the first of the modes.
17. The memory system of claim 10, wherein the third of the modes uses programming pulses of lesser amplitude than the first of the modes.
18. A method of operating a memory system comprising a memory having a rewritable data storage portion and a controller for managing data stored in the memory and controlling the transfer of data between the memory system and a host to which the memory system is connected where the controller can operate the memory system according to a plurality of modes, each of the modes having a different level of performance for operations involving the writing of data, including a second mode of higher performance than a first mode, the method comprising:
operating the memory according to the first of the modes;
subsequently determining by the controller of a system related high latency situation;
in response to said determining of a system related high latency situation, the controller selecting a second of the modes for the for operation of the memory system; and
subsequently operating the memory according to the second of the modes instead of the first of the modes.
19. The method of claim 18, wherein said high latency situation is an error during programming.
20. The method of claim 18, wherein said high latency situation is an error during a data relocation operation.
21. The method of claim 18, wherein said high latency situation is a garbage collection operation.
22. The method of claim 18, wherein the second of the modes uses a lower level of error detection and correction than the first of the modes.
23. The method of claim 18, wherein the second of the modes uses a faster programming sequence than the first of the modes.
24. The method of claim 18, wherein the second of the modes uses a faster clock speed than the first of the modes.
25. The method of claim 18, wherein the second of the modes uses programming pulses of longer duration than the first of the modes.
26. The method of claim 18, wherein the second of the modes uses programming pulses of greater amplitude than the first of the modes.
27. The method of claim 18, further comprising:
determining by the controller of an additional system related situation; and
in response to said determining an additional system related situation, operating the memory according to a third of the modes in response to an additional system related situation, wherein the third of the modes is of greater reliability than the first of the modes.
28. The memory system of claim 27, wherein the additional system related situation is partial page programming.
29. The memory system of claim 27, wherein the additional system related situation is a low voltage condition.
30. The memory system of claim 27, wherein the third of the modes utilizes a higher degree of error detection and correction than the first of the modes.
31. The memory system of claim 27, wherein the third of the modes utilizes a slower programming sequence than the first of the modes.
32. The memory system of claim 27, wherein the third of the modes utilizes a slower clock rate than the first of the modes.
33. The memory system of claim 27, wherein the third of the modes utilizes programming pulses of shorter duration than the first of the modes.
34. The memory system of claim 27, wherein the third of the modes uses programming pulses of lesser amplitude than the first of the modes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory device comprising:
a first sense amplifier that is positioned in a first region and amplifies signals from a memory cell in the first region;
a second sense amplifier that is positioned in a second region and amplifies signals from a memory cell in the second region;
a bus that is connected to the first and second sense amplifiers and passes through the first and second regions;
a first latch that is positioned in the second region and is connected to the bus, and
a second latch that is positioned in the second region and is connected to the bus.
2. The semiconductor memory device according to claim 1, further comprising:
a second bus that transfers signals between the first and second latches and a pad of the semiconductor memory device.
3. The semiconductor memory device according to claim 2, wherein the bus includes a first bus and a second bus, and the semiconductor memory device further comprises:
a third latch that is connected to the first sense amplifier through the first bus and is connected to the second sense amplifier through the second bus.
4. The semiconductor memory device according to claim 3, further comprising:
a control circuit that conducts data transfer from the first sense amplifier to the third latch via the first bus and data transfer from the third latch to the first latch via the second bus or data transfer from the second sense amplifier to the second latch in parallel.
5. The semiconductor memory device of claim 4, wherein
the first and second sense amplifiers and the bus are positioned between the memory cell and a substrate.
6. A semiconductor memory device comprising:
a plurality of memory cells including a plurality of planes therein;
a data bus extending in communication with at least two of the plurality of planes; and
within the at least two of the plurality of planes, a plurality of bit lines and a plurality of sense amplifiers, each bit line selectively connectable to the plurality of sense amplifiers at a first side thereof, wherein the second side of the sense amplifiers is connected to the data bus extending in communication with at least two of the plurality of planes.
7. The semiconductor memory device of claim 6, wherein a sense amplifier includes a sense amplifying circuit.
8. The semiconductor memory device of claim 7, wherein the sense amplifier includes at least one latch operatively connected thereto and intermediate of the sense amplifying circuit and the data bus.
9. The semiconductor memory of claim 6, wherein
a first plane and a second plane are positioned such that an IO interface is accessible from a side of each plane;
each of the first and second planes include a plurality of sense amplifiers 0 to n interconnected with a plurality of bit lines 0 to n, where n is a whole number; and
the nth sense amplifier of the plurality of sense amplifiers of the first plane is located adjacent to the first plane located adjacent to the second plane, and the nth sense amplifier of the plurality of sense amplifiers of the second plane is located adjacent to the second plane located adjacent to the first plane.
10. The semiconductor memory of claim 9, further including a receiver located between the first and second planes.
11. The semiconductor memory of claim 9, further including a first receiver on a portion of the data bus extending from the first plane and a second receiver on a portion of the data bus extending from the second plane.
12. The semiconductor memory device of claim 6, wherein the data bus extends from a 0 plane through an nth plane, where n is a whole number.
13. The semiconductor device of claim 12, further including a receiver interconnected with the data bus on, or adjacent to, the nth plane.
14. The semiconductor memory device of claim 6, further including a temporary latch disposed in series communication with the data bus.
15. The semiconductor device of claim 14, wherein the temporary latch is disposed in a plane.
16. A method of configuring a semiconductor memory device, comprising:
providing a first plane of the memory including a plurality of bit lines interconnected with a plurality of sense amplifiers;
providing a second plane of the memory including a plurality of bit lines interconnected with a plurality of sense amplifiers;
providing a data bus configured to interconnect to the first plane and the second plane.
17. The method of claim 16, further including the step of providing a receiver intermediate of the first plane and the second plane.
18. The method of claim 16, further including the steps of providing a first receiver intermediate of the first plane and the interface, and a second receiver intermediate of the second plane and the interface.
19. The method of claim 16, further including the steps of:
extending the data bus through the first and the second pages; and
providing a latch at the terminus of the data bus.
20. The method of claim 19, further including the step of interconnecting the latch to the interface.