What is claimed is:
1. A storage device with at least, a head for writing data in or reading data from a storage medium, accommodated in an enclosure thereof, said storage device comprising:
an external recording circuit provided outside said enclosure for outputting write data comprising parallel data; and
an internal recording circuit provided inside said, enclosure for receiving write data comprising parallel data supplied from said external recording circuit; wherein said internal recording circuit comprising at least:
a parallel-to-serial conversion circuit for converting the received write data comprising parallel data to serial data;
a write compensation circuit for changing a timing for writing data having been converted to serial data; and
a write amplifier for switching a polarity of a recording current to be supplied to said head according to the serial write data of which a write timing is adjusted.
2. A storage device according to claim 1; wherein said internal recording circuit is based on the PRML detection system, and said write compensation circuit is a circuit for previously compensating non-linear recording distortion occurring to a recording medium by changing a timing for writing.
3. A storage device according to claim 1; wherein said internal recording circuit is based on the PRML detection system, further has an internal reproducing circuit provided inside the enclosure and also has an external reproducing circuit provided outside the enclosure, and said internal reproducing circuit comprises:
an equalizer. circuit for executing an equalizing operation for a read signal amplified by said preamplifier; and
a serial-to-parallel conversion circuit for converting read data comprising the serial data having been subjected to an equalizing operation to parallel data and outputting the parallel data to said external reproducing circuit.
4. A storage device according to claim 1; wherein said internal recording circuit further comprises an encoder circuit for encoding the serial data converted by said parallel-to-serial conversion circuit.
5. A storage device according to claim 1; wherein said write compensation circuit is a circuit for previously compensating a peak shift due to interference between waveforms by changing a timing for writing.
6. A storage device according to claim 1; wherein said storage device further comprising at least:
an internal reproducing circuit provided inside the enclosure and also having an external reproducing circuit provided outside the enclosure; wherein said internal reproducing circuit comprises:
a preamplifier for amplifying a read signal detected by said head;
a decoder circuit for decoding the read signal amplifier by said preamplifier; and
a serial-to-parallel conversion circuit for converting the read data comprising the decoded serial data to parallel data and outputting the parallel data to said external reproducing circuit.
7. A storage device according to claim 1; wherein said internal recording circuit is based on the PRML detection system and comprises:
a precoder circuit for previously executing an operation reverse to an equalizing operation executed to read data when reproducing the read data to the serial data converted by said parallel-to-serial conversion circuit.
8. A storage device according to claim 7; wherein said internal recording circuit is based on the PRML detection system, further has an internal reproducing circuit provided inside the enclosure and also has an external reproducing circuit provided outside the enclosure, and said internal reproducing circuit comprises:
an equalizer circuit for executing an equalizing operation for a read signal amplified by said preamplifier; and
a serial-to-parallel conversion circuit for converting read data comprising the serial data having been subjected to an equalizing operation to parallel data and outputting the parallel data to said external reproducing circuit.
9. A storage device according to claim 7; wherein said internal recording circuit is based on the PRML detect ion system, and said write compensation circuit is a circuit for previously compensating non-linear recording distortion occurring to a recording medium by changing a timing for writing.
10. A storage device according to claim 9; wherein said internal recording circuit is based on the PRML detection system, further has an internal reproducing circuit provided inside the enclosure and also has an external reproducing circuit provided outside the enclosure, and said internal reproducing circuit comprises:
an equalizer circuit for executing an equalizing operation for a read signal amplified by said preamplifier; and
a serial-to-parallel conversion circuit for converting read data comprising the serial data having been subjected to an equalizing operation to parallel data and outputting the parallel data to said external reproducing circuit.
11. A storage device according to claim 1; wherein said internal recording circuit further comprises:
a synthesizer circuit for generating a timing signal and a clock signal each for writing data.
12. A storage device according to claim 1; wherein some or all of the circuits constituting said internal recording circuit andor the internal reproducing circuit are provided on a carriage supporting said head thereon.
13. A storage device according to claim 12; wherein said internal recording circuit andor internal reproducing circuit is formed with a single semiconductor chip.
14. A storage device according to claim 1; wherein some or all of the circuits constituting said internal recording circuit andor internal reproducing circuit are connected to a section between a carriage supporting the head and the external recording circuit andor said external reproducing circuit and are also provided on a flexible printed circuit board provided inside said enclosure.
15. A storage device according to claim 14; wherein said internal recording circuit andor internal reproducing circuit is formed with a single semiconductor chip.
16. A storage device with at least a storage medium, a head for writing data in or reading data from said storage medium, and a motor for driving said storage medium and head accommodated in an enclosure thereof, said storage device comprising:
an external recording circuit provided outside said enclosure for converting write data comprising parallel data to serial data and outputting the serial data; and
an internal recording circuit provided inside said enclosure for receiving write data comprising the serial data supplied from said external recording circuit; wherein said internal recording circuit comprises:
a correcting circuit for correcting rise and fall of a received write data pulse; and
a write amplifier for switching a polarity of a recording current to be supplied to said head according to the amplified write data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system, comprising:
a client device configured to transmit data to a host device, receive data from a host device, determine client clock phase information between a local client clock signal generated from a system timing signal and data received from the host device, and transmit client clock phase information to the host device during an electrical turnaround time between read and write operations over a data bus coupling the client device and the host device; and
a host device configured to receive the client clock phase information from the client device, the host device comprising shared data synchronization resources that use the client clock phase information to adjust a host clock for transmitting data to the at least one client device, wherein the shared resources are shared between transmit and receive functions of the host device.
2. The system of claim 1, wherein said host device further comprises a shared phased interpolator that adjusts a host clock based at least on the client clock phase information.
3. A phase detector for receiving data on a data link and for receiving a local clock signal during an electrical turnaround time between read and write operations over a data bus coupling a client device and a host device, said detector comprising:
a sampler that detects the relationship between the local clock signal and the received data and generates a phase information signal indicative of said detected relationship;
a logic unit for encoding the phase information signal as clock phase information; and
a transmitter that transmits the clock phase information,
wherein the clock phase information enables adjusting a host clock for transmitting data to at least one client device.
4. The detector of claim 3, wherein said phase information signal is a two bit encoded signal.
5. The detector of claim 3, wherein said logic identifies the local clock signal as one of early, late and aligned.
6. The detector of claim 3, wherein said logic is suitable for controlling a shared phase interpolator, which interpolator adjusts a local host clock.
7. The detector of claim 3, wherein said logic comprises phase control logic.
8. The detector of claim 3, wherein said detected relationship is a phase relationship.
9. The detector of claim 3, wherein the local clock signal is detected using an active edge.
10. The detector of claim 3, wherein the data is detected using a data eye.
11. The detector of claim 3, wherein the determined logic is transmitted during periods when the data link is not in use.
12. A host device for correcting a phase relationship determined at a client device between received data of the client device on a data link and a local clock signal of the client device, said host device comprising:
a receiver that receives logic during an electrical turnaround time between read and write operations over a data bus coupling the client device and the host device, wherein said received logic is determined from a phase information signal derived at the client device by comparing the phase relationship of a system timing signal generated local client clock signal and data received from the host device, wherein the phase information signal is indicative of the relationship between the client device local clock signal and client device received data; and
a synchronizer that determines an offset from the received logic and adjusts a host clock signal relative to said determined offset.
13. The device of claim 12, wherein the logic identifies the local client clock signal as one of early, late and aligned.
14. The device of claim 12, wherein said logic comprises phase control logic.
15. The device of claim 12, wherein said detected relationship is a phase relationship.
16. The device of claim 12, wherein the client device received data is detected using the data eye.
17. The device of claim 12, wherein the logic is received during periods when the data link is not in use.