1. A method of designing an integrated circuit having latches, said method comprising:
preparing a logical design of logic devices and latches; and
creating a physical design by positioning said logic devices and said latches within said integrated circuit based on said logical design,
wherein said creating of said physical design further comprises eliminating redundant latches, wherein redundant latches comprise latches which do not transition during the same clock cycle, do not relate to the same logical function, are in the same clock domain, and are within a given physical proximity of each other.
2. The method in claim 1, further comprising determining whether latches transition during the same clock cycle by running a simulation of an initial physical design and recording the latches that transition during each clock cycle.
3. The method in claim 2, wherein said process of determining whether latches transition during the same clock cycle further comprises determining whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle.
4. The method in claim 1, wherein said process of eliminating redundant latches comprises replacing at least two redundant latches with a single latch.
5. The method in claim 1, wherein said process of eliminating redundant latches produces a revised physical design, and said process further comprises testing said revised physical design to determine whether said revised physical design performs as expected.
6. The method in claim 1, further comprising determining whether said latches relate to the same logical function by recording which latches are associated with each logical function in said logical design.
7. The method in claim 1, further comprising determining whether said latches are in the same clock domain by recording which latches are associated with each clock domain in said logical design.
8. A method of designing an integrated circuit having latches, said method comprising:
preparing a logical design of logic devices and latches;
creating an initial physical design by positioning said logic devices and said latches within said integrated circuit based on said logical design;
preparing a database of transition times for said latches by running a simulation of an initial physical design and recording the clock cycle in which each latch transitions;
altering said initial physical design to eliminate redundant latches which do not transition during the same clock cycle.
9. The method in claim 8, wherein said altering of said initial physical design further considers whether latches relate to the same logical function, whether latches are in the same clock domain, and whether latches are within a given physical proximity of each other.
10. The method in claim 8, wherein said altering of said initial physical design further considers whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle.
11. The method in claim 8, wherein said altering of said initial physical design to eliminate redundant latches comprises replacing at least two redundant latches with a single latch.
12. The method in claim 8, wherein said altering of said initial physical design to eliminate redundant latches produces a revised physical design, and said process further comprises testing said revised physical design to determine whether said revised physical design performs as expected.
13. The method in claim 8, further comprising determining whether said latches relate to the same logical function by recording, in said database, which latches are associated with each logical function in said logical design.
14. The method in claim 8, further comprising adding selection logic connected to said latches, wherein said selection logic locks a non-active output to a known logical state when another output is active.
15. A method of designing an integrated circuit having latches, said method comprising:
preparing a logical design of logic devices and latches;
creating an initial physical design by positioning said logic devices and said latches within said integrated circuit based on said logical design;
preparing a database of transition times for said latches by running a simulation of an initial physical design and recording the clock cycle in which each latch transitions;
altering said initial physical design to eliminate redundant latches which do not transition during the same clock cycle, do not relate to the same logical function, are in the same clock domain, and are within a given physical proximity of each other.
16. The method in claim 15, wherein said altering of said initial physical design further considers whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle.
17. The method in claim 15, wherein said altering of said initial physical design to eliminate redundant latches comprises replacing at least two redundant latches with a single latch.
18. The method in claim 15, wherein said altering of said initial physical design to eliminate redundant latches produces a revised physical design, and said process further comprises testing said revised physical design to determine whether said revised physical design performs as expected.
19. The method in claim 15, further comprising determining whether said latches relate to the same logical function by recording, in said database, which latches are associated with each logical function in said logical design.
20. The method in claim 15, further comprising determining whether said latches are in the same clock domain by recording, in said database, which latches are associated with each clock domain in said logical design.
21. A method of designing an integrated circuit having latches, said method comprising:
preparing a logical design of logic devices and latches;
creating an initial physical design by positioning said logic devices and said latches within said integrated circuit based on said logical design;
preparing a database of transition times for said latches by running a simulation of an initial physical design and recording the clock cycle in which each latch transitions; determining whether said latches are in the same clock domain by recording, in said database, which latches are associated with each clock domain in said logical design; altering said initial physical design to eliminate redundant latches which do not transition during the same clock cycle, do not relate to the same logical function, are in the same clock domain, and are within a given physical proximity of each other,
wherein said process of altering said initial physical design to eliminate redundant latches produces a revised physical design, and said process further comprises testing said revised physical design to determine whether said revised physical design performs as expected.
22. The method in claim 21, wherein said altering of said initial physical design further considers whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle.
23. The method in claim 21, wherein said altering of said initial physical design to eliminate redundant latches comprises replacing at least two redundant latches with a single latch.
24. A method of designing an integrated circuit having latches, said method comprising:
preparing a logical design of logic devices and latches;
creating an initial physical design by positioning said logic devices and said latches within said integrated circuit based on said logical design,
eliminating redundant latches from said initial physical design to create a revised physical design, and adding selection logic connected to said latches in said revised physical design, wherein said selection logic includes outputs equal in number to the number of latches in said initial physical design and said selection logic locks a non-active output to a known logical state when a corresponding output is active.
25. The method in claim 24, wherein said adding of said selection logic comprises adding inverters and logical AND devices connected to said latches to make said outputs mutually exclusive.
26. The method in claim 24, wherein said adding of said selection logic permits one control signal to control a series of outputs similarly.
27. The method in claim 24, wherein redundant latches comprise latches which do not transition during the same clock cycle, do not relate to the same logical function, are in the same clock domain, and are within a given physical proximity of each other.
28. The method in claim 27, further comprising determining whether latches transition during the same clock cycle by running a simulation of an initial physical design and recording the latches that transition during each clock cycle.
29. The method in claim 28, wherein said process of determining whether latches transition during the same clock cycle further comprises determining whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle.
30. The method in claim 24, wherein said process of eliminating redundant latches comprises replacing at least two redundant latches with a single latch.
31. The method in claim 24, further comprising testing said revised physical design to determine whether said revised physical design performs as expected.
32. The method in claim 27, further comprising determining whether said latches relate to the same logical function by recording which latches are associated with each logical function in said logical design.
33. The method in claim 27, further comprising determining whether said latches are in the same clock domain by recording which latches are associated with each clock domain in said logical design.
34. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method of designing an integrated circuit having latches, said method comprising:
preparing a logical design of logic devices and latches;
creating an initial physical design by positioning said logic devices and said latches within said integrated circuit based on said logical design;
preparing a database of transition times for said latches by running a simulation of an initial physical design and recording the clock cycle in which each latch transitions;
altering said initial physical design to eliminate redundant latches which do not transition during the same clock cycle.
35. The program storage device in claim 34, wherein said altering of said initial physical design further considers whether latches relate to the same logical function, whether latches are in the same clock domain, and whether latches are within a given physical proximity of each other.
36. The program storage device in claim 34, wherein said altering of said initial physical design further considers whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle.
37. The program storage device in claim 34, wherein said altering of said initial physical design to eliminate redundant latches comprises replacing at least two redundant latches with a single latch.
38. The program storage device in claim 34, wherein said altering of said initial physical design to eliminate redundant latches produces a revised physical design, and said process further comprises testing said revised physical design to determine whether said revised physical design performs as expected.
39. The program storage device in claim 34, wherein said method further comprises determining whether said latches relate to the same logical function by recording, in said database, which latches are associated with each logical function in said logical design.
40. The program storage device in claim 34, wherein said method further comprises determining whether said latches are in the same clock domain by recording, in said database, which latches are associated with each clock domain in said logical design.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for representing in a graphical model an interface between electronic components of a computational hardware device, the method comprising:
providing, in a modeling environment, a graphical model representing a design for implementation in a first computational hardware device having at least a first electronic component and a second electronic component, the first electronic component and the second electronic component separated by a first interface boundary representing the interface between electronic components;
identifying an interface point between a first part of the graphical model representing a portion of the design associated with the first electronic component and a second part of the graphical model representing a portion of the design associated with a second electronic component; and
graphically representing via an interface indicator at the interface point in the graphical model a component interface between the first electronic component and the second electronic component, wherein the interface indicator can represent at least one type of component interface of one or more component interface types.
2. The method of claim 1, comprising identifying a component interface type from one or more component interface types to associate with the interface indicator without changing the graphical representation of one of the graphical model and the interface indicator.
3. The method of claim 1, comprising associating a component interface type from one or more component interface types with the interface indicator while maintaining the graphical representation of one of the graphical model and the interface indicator.
4. The method of claim 1, comprising associating the interface indicator with one component interface type of one or more component interfaces between electronic components different than one of the first electronic component and the second electronic component, while maintaining the graphical representation of the interface indicator.
5. The method of claim 1, wherein the design of the graphical model can be implemented on a second computational hardware device without changing the graphical representation of one of the graphical model and the interface indicator, the second computational hardware device having one or more different component interfaces than the first computational hardware device.
6. The method of claim 1, wherein the design of the graphical model can be implemented in a second computational hardware device without changing the graphical representation of one of the graphical model and the interface indicator, the second computational hardware device having one of the same electronic components as the first computational hardware device and electronic components different than the first computational hardware device.
7. The method of claim 1, comprising graphically representing via a plurality of interface indicators a plurality of component interfaces between electronic components represented by parts of the graphical model.
8. The method of claim 1, wherein one of the first electronic component and the second electronic component comprises one of a processor, a field programmable gate array, an application specific integrated circuit, and a programmable logic device.
9. The method of claim 1, wherein one of a first portion of code suitable for implementation on the first component, and a second portion of code suitable for implementation on the second component, is automatically generated from the block diagram model to provide an implementation of the component interface between the first electronic component and the second electronic component represented by the interface indicator.
10. The method of claim 1, comprising configuring, in the modeling environment, a type of the component interface associated with the interface indicator, the type obtained from one or more of the following:
one or more component interface types listed with the modeling environment,
a topology of one or more computational hardware devices listed with the modeling environment,
a library of one or more component interfaces readable by the modeling environment, and
a reference configured in the modeling environment to component interface code provided by a user.
11. A method for generating code from a graphical model representing a component interface between electronic components in a computational hardware device, the method comprising:
receiving a graphical model having an interface indicator representing a component interface between a first electronic component and a second electronic component of a computational hardware device, a first part of the graphical model represents at least a portion of a design to be implemented in the first electronic component, and a second part of the graphical model represents at least a portion of a design to be implemented in the second electronic component, the first electronic component and the second electronic component separated by a first interface boundary;
determining the component interface type represented by the interface indicator, wherein the interface indicator can represent at least one component interface type of one or more component interface types;
generating a first set of code for the first part of the graphical model that includes a first portion of the component interface to execute on the first electronic component, and
generating a second set of code for the second part of the graphical model including a second portion of the component interface to execute on the second electronic component.
12. The method of claim 11, wherein the first set of code further comprises code representative of a portion of functionality represented by the first part of the graphical model, and the second set of code further comprises code representative of a portion of functionality represented by the second part of the graphical model.
13. The method of claim 11, wherein one of the first portion of code and the second portion of code comprises code determined by a type of component interface associated with the interface indicator of the graphical model.
14. The method of claim 11, wherein one of the first electronic component and the second electronic component comprises one of a processor, a field programmable gate array, an application specific integrated circuit, and a programmable logic device.
15. The method of claim 11, comprising:
invoking a building of one of the first set of code and the second set of code into a program to execute on one of the first electronic component and the second electronic component.
16. The method of claim 11, comprising:
generating a portion of the code for the component interface between the first electronic component and the second electronic component by linking in a device driver.
17. The method of claim 11, comprising generating code for a plurality of component interfaces represented by a plurality of interface indicators in the graphical model.
18. A method for representing in a graphical model a component interface between electronic components of a computational hardware device and generating code for the component interface from the graphical model, the method comprising:
providing, in a modeling environment, a graphical model representing a design for implementation in a first computational hardware device having at least a first electronic component and a second electronic component, a first part of the graphical model represents a portion of the design for implementation in the first electronic component, and a second part of the graphical model represents a portion of the design for implementation in the second electronic component, the first electronic component and the second electronic component separated by a first interface boundary representing the component interface between electronic components;
graphically representing via an interface indicator between a first part and a second part of the graphical model a component interface for implementation between the first electronic component associated with the first part and the second electronic component associated with the second part; and
generating code for the first component interface between the first electronic component and the second electronic component.
19. The method of claim 18, wherein generating code comprises generating one of a first set of code for the first part of the graphical model comprising a first portion of the component interface to execute on the first component, and a second set of code for the second part of the graphical model comprising a second portion of the component interface to execute on the second component.
20. The method of claim 18, comprising identifying a component interface type from one or more component interface types to associate with the interface indicator without changing the graphical representation of one of the graphical model and the interface indicator.
21. The method of claim 18, comprising associating a component interface type from one or more component interface types with the interface indicator while maintaining the graphical representation of one of the graphical model and the interface indicator.
22. The method of claim 18, comprising associating the interface indicator with one component interface type of one or more component interfaces between electronic components different than one of the first electronic component and the second electronic component, while maintaining the graphical representation of the interface indicator.
23. The method of claim 18, wherein the design of the graphical model can be implemented on a second computational hardware device without changing the graphical representation of one of the graphical model and the interface indicator, the second computational hardware device having one or more different component interfaces than the first computational hardware device.
24. The method of claim 18, wherein the design of the graphical model can be implemented in a second computational hardware device without changing the graphical representation of one of the graphical model and the interface indicator, the second computational hardware device having one of the same electronic components as the first computational hardware device and electronic components different than the first computational hardware device.
25. The method of claim 18, comprising graphically representing via a plurality of interface indicators a plurality of component interfaces between electronic components represented by parts of the graphical model.
26. The method of claim 25, comprising generating code for each of the plurality of component interfaces.
27. The method of claim 18, wherein one of the first component and the second component comprises one of a processor, a field programmable gate array, an application specific integrated circuit, and a programmable logic device.
28. The method of claim 18, comprising configuring, in the modeling environment, a type of the first component interface associated with the first boundary, the type obtained from one or more of the following:
one or more component interface types listed with the modeling environment,
a topology of one or more computational hardware devices listed with the modeling environment,
a library of one or more component interfaces readable by the modeling environment, and
a reference configured in the modeling environment to component interface code provided by a user.
29. The method of claim 18, comprising:
invoking a building of one of the first set of code and the second set of code into a program to execute on one of the first electronic component and the second electronic component.
30. The method of claim 18, comprising:
generating a portion of the code of the first component interface between the first electronic component and the second electronic component by linking in a device driver.
31. A system for representing in a graphical model a component interface between electronic components of a computational hardware device and generating code for the component interface from the graphical model, the system comprising:
a graphical modeling environment providing a graphical model representing a design for implementation in a first computational hardware device having at least a first electronic component and a second electronic component, a first part of the graphical model represents a portion of the design for implementation in the first electronic component, and a second part of the graphical model represents a portion of the design for implementation in a second electronic component, the first electronic component and the second electronic component separated by a first interface boundary representing the component interface between electronic components;
a configuration mechanism to graphically represent via an interface indicator between the first part and the second part of the graphical model a component interface between the first electronic component associated with the first part and the second electronic component associated with the second part; and
a code generator receiving the graphical model, and generating code for the component interface between the first electronic component and the second electronic component.
32. The system of claim 31, wherein one of the graphical modeling environment and the code generator executes on one of a first computing device and a second computing device.
33. The system of claim 31, wherein the code generator generates one of a first set of code and a second set of code comprising one of a first portion and a second portion of the component interface.
34. The system of claim 31, wherein the code generator invokes a building of one of the first set of code and the second set of code into executable instructions to execute on one of the first electronic component and the second electronic component.
35. The system of claim 31, wherein the configuration mechanism provides a user interface to define a type of the first component interface associated with the interface indicator, the configuration mechanism obtains a type of the component interface from one or more of the following:
one or more component interface types listed with the modeling environment,
a topology of one or more computational hardware devices listed with the modeling environment,
a library of one or more component interfaces readable by the modeling environment, and
a reference configured in the modeling environment to component interface code provided by a user.
36. The system of claim 31, wherein one of the first component and the second component comprises one of a processor, a field programmable gate array, an application specific integrated circuit, and a programmable logic device.
37. The system of claim 31, wherein the code generator obtains a portion of the first component interface between the first electronic component and the second electronic component by linking in a device driver.
38. A device readable medium holding device readable instructions for a method of representing in a graphical model an interface between electronic components of a computational hardware device, the method comprising:
providing, in a modeling environment, a graphical model representing a design for implementation in a first computational hardware device having at least a first electronic component and a second electronic component, the first electronic component and the second electronic component separated by a first interface boundary;
identifying an interface point between a first part of the graphical model representing a portion of the design associated with the first electronic component and a second part of the graphical model representing a portion of the design associated with a second electronic component; and
graphically representing via an interface indicator at the interface point in the graphical model a component interface between the first electronic component and the second electronic component, wherein the interface indicator can represent at least one type of component interface of one or more component interface types.
39. The medium of claim 38, comprising identifying a component interface type from one or more component interface types to associate with the interface indicator without changing the graphical representation of one of the graphical model and the interface indicator.
40. The medium of claim 38, comprising associating a component interface type from one or more component interface types with the interface indicator while maintaining the graphical representation of one of the graphical model and the interface indicator.
41. The medium of claim 38, comprising associating the interface indicator with one component interface type of one or more component interfaces between electronic components different than one of the first electronic component and the second electronic component, while maintaining the graphical representation of the interface indicator.
42. The medium of claim 38, wherein the design of the graphical model can be implemented on a second computational hardware device without changing the graphical representation of one of the graphical model and the interface indicator, the second computational hardware device having one or more different component interfaces than the first computational hardware device.
43. The medium of claim 38, wherein the design of the graphical model can be implemented in a second computational hardware device without changing the graphical representation of one of the graphical model and the interface indicator, the second computational hardware device having one of the same electronic components as the first computational hardware device and electronic components different than the first computational hardware device.
44. The medium of claim 38, comprising graphically representing via a plurality of interface indicators a plurality of component interfaces between electronic components represented by parts of the graphical model.
45. The medium of claim 38, wherein one of the first electronic component and the second electronic component comprises one of a processor, a field programmable gate array, an application specific integrated circuit, and a programmable logic device.
46. The medium of claim 38, wherein one of a first portion of code suitable for implementation on the first component, and a second portion of code suitable for implementation on the second component, is automatically generated from the block diagram model to provide an implementation of the component interface between the first electronic component and the second electronic component represented by the interface indicator.
47. The medium of claim 38, comprising configuring, in the modeling environment, a type of the component interface associated with the interface indicator, the type obtained from one or more of the following:
one or more component interface types listed with the modeling environment,
a topology of one or more computational hardware devices listed with the modeling environment,
a library of one or more component interfaces readable by the modeling environment, and
a reference configured in the modeling environment to component interface code provided by a user.
48. A device readable medium holding device readable instructions for a method of generating code from a graphical model for an interface between electronic components in a computational hardware device, the method comprising:
receiving a graphical model having an interface indicator representing a component interface between a first electronic component and a second electronic component of a computational hardware device, a first part of the graphical model represents at least a portion of a design to be implemented in the first electronic component, and a second part of the graphical model represents at least a portion of a design to be implemented in the second electronic component, the first electronic component and the second electronic component separated by a first interface boundary representing the component interface between electronic components;
determining the component interface type represented by the interface indicator, wherein the interface indicator can represent at least one component interface type of one or more component interface types;
generating a first set of code for the first part of the graphical model that includes a first portion of the component interface to execute on the first electronic component, and
generating a second set of code for the second part of the graphical model including a second portion of the component interface to execute on the second electronic component.
49. The medium of claim 48, wherein the first set of code further comprises code representative of a portion of functionality represented by the first part of the graphical model, and the second set of code further comprises code representative of a portion of functionality represented by the second part of the graphical model.
50. The medium of claim 48, wherein one of the first portion of code and the second portion of code comprises code determined by a type of component interface associated with the interface indicator of the graphical model.
51. The medium of claim 48, comprising generating code for a plurality of component interfaces represented by a plurality of interface indicators in the graphical model.
52. The medium of claim 48, wherein one of the first electronic component and the second electronic component comprises one of a processor, a field programmable gate array, an application specific integrated circuit, and a programmable logic device.
53. The medium of claim 48, comprising:
invoking a building of one of the first set of code and the second set of code into a program to execute on one of the first electronic component and the second electronic component.
54. The medium of claim 48, comprising:
generating a portion of the code for the component interface between the first electronic component and the second electronic component by linking in a device driver.
55. A device readable medium holding device readable instructions for a method for representing in a graphical model a component interface between electronic components of a computational hardware device and generating code for the component interface from the graphical model, the method comprising:
providing, in a modeling environment, a graphical model representing a design for implementation in a first computational hardware device having at least a first electronic component and a second electronic component, a first part of the graphical model represents a portion of the design for implementation in the first electronic component, and a second part of the graphical model represents a portion of the design for implementation in the second electronic component, the first electronic component and the second electronic component separated by a first interface boundary representing the component interface between electronic components;
graphically representing via an interface indicator between a first part and a second part of the graphical model a component interface for implementation between the first electronic component associated with the first part and the second electronic component associated with the second part; and
generating code for the first component interface between the first electronic component and the second electronic component.
56. The medium of claim 55, wherein generating code comprises generating one of a first set of code for the first part of the graphical model comprising a first portion of the component interface to execute on the first component, and a second set of code for the second part of the graphical model comprising a second portion of the component interface to execute on the second component.
57. The medium of claim 55, comprising identifying a component interface type from one or more component interface types to associate with the interface indicator without changing the graphical representation of one of the graphical model and the interface indicator.
58. The medium of claim 55, comprising associating a component interface type from one or more component interface types with the interface indicator while maintaining the graphical representation of one of the graphical model and the interface indicator.
59. The medium of claim 55, comprising associating the interface indicator with one component interface type of one or more component interfaces between electronic components different than one of the first electronic component and the second electronic component, while maintaining the graphical representation of the interface indicator.
60. The medium of claim 55, wherein the design of the graphical model can be implemented on a second computational hardware device without changing the graphical representation of one of the graphical model and the interface indicator, the second computational hardware device having one or more different component interfaces than the first computational hardware device.
61. The medium of claim 55, wherein the design of the graphical model can be implemented in a second computational hardware device without changing the graphical representation of one of the graphical model and the interface indicator, the second computational hardware device having one of the same electronic components as the first computational hardware device and electronic components different than the first computational hardware device.
62. The medium of claim 55, comprising generating code for a plurality of component interfaces represented by a plurality of interface indicators in the graphical model.
63. The medium of claim 62, wherein one of the first component and the second component comprises one of a processor, a field programmable gate array, an application specific integrated circuit, and a programmable logic device.
64. The medium of claim 55, comprising configuring, in the modeling environment, a type of the first component interface associated with the first boundary, the type obtained from one or more of the following:
one or more component interface types listed with the modeling environment,
a topology of one or more computational hardware devices listed with the modeling environment,
a library of one or more component interfaces readable by the modeling environment, and
a reference configured in the modeling environment to component interface code provided by a user.
65. The medium of claim 55, comprising:
invoking a building of one of the first set of code and the second set of code into a program to execute on one of the first electronic component and the second electronic component.
66. The medium of claim 55, comprising:
generating a portion of the code of the first component interface between the first electronic component and the second electronic component by linking in a device driver.
67. A distribution system for transmitting device readable instructions for a method of representing in a graphical model an interface between electronic components of a computational hardware device, the method comprising:
providing, in a modeling environment, a graphical model representing a design for implementation in a first computational hardware device having at least a first electronic component and a second electronic component, the first electronic component and the second electronic component separated by a first interface boundary representing the interface between electronic components;
identifying an interface point between a first part of the graphical model representing a portion of the design associated with the first electronic component and a second part of the graphical model representing a portion of the design associated with a second electronic component; and
graphically representing via an interface indicator at the interface point in the graphical model a component interface between the first electronic component and the second electronic component, wherein the interface indicator can represent at least one type of component interface of one or more component interface types.
68. A distribution system for transmitting readable instructions for a method of generating code from a graphical model for an interface between electronic components in a computational hardware device, the method comprising:
receiving a graphical model having an interface indicator representing a component interface between a first electronic component and a second electronic component of a computational hardware device, a first part of the graphical model represents at least a portion of a design to be implemented in the first electronic component, and a second part of the graphical model represents at least a portion of a design to be implemented in the second electronic component, the first electronic component and the second electronic component separated by a first interface boundary representing the interface between electronic components;
determining the component interface type represented by the interface indicator, wherein the interface indicator can represent at least one component interface type of one or more component interface types;
generating a first set of code for the first part of the graphical model that includes a first portion of the component interface to execute on the first electronic component, and
generating a second set of code for the second part of the graphical model including a second portion of the component interface to execute on the second electronic component.