1. A graphics plotting apparatus which performs a rendering process, comprising:
a logic circuit block;
a memory block having a capacity sufficient to store display data to be displayed wherein the logic circuit block and the memory block are built in the same chip;
an input buffer provided at an input portion of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
an initialization arithmetic operation circuit block for linear interpolation operation arranged adjacent the input buffer; and
a linear interpolation processing circuit block arranged adjacent the initialization arithmetic operation block for linear interpolation operation wherein the linear interpolation processing circuit block performs processing of pixels within a fixed united range which is set independently of a form of a display memory and independently of a page boundary of the display memory.
2. A graphics plotting apparatus which performs a rendering process, comprising:
a logic circuit block;
a memory block having a capacity sufficient to store display data to be displayed wherein the logic circuit block and the memory block are built in the same chip;
an input buffer provided at an input portion of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive; and
a first-in first-out buffer disposed on a receiving side of a bus between circuit blocks which are physically separated from each other, a signal for notification that the first-in first-out buffer will be fully occupied soon being transmitted to a data transmitting side of one of the circuit blacks so that stopping of transfer from the data transmitting side circuit block may be performed from the other data receiving side circuit block.
3. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit, block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer.
4. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a tendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, and wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip.
5. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
a register arranged between the memory block and the texture processing circuit block, operation of the register being uncontrollable from the texture processing circuit block wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip.
6. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the liner interpolation processing circuit block is arranged adjacent the initialization arithmetic operation block for linear interpolation operation wherein the texture processing circuit block is, arranged adjacent the linear interpolation operation processing circuit block, and wherein the texture processing circuit block has a block size greater than respective block sizes of the initialization arithmetic operation circuit block for linear interpolation operation and the linear interpolation processing circuit block.
7. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic from including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogenous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the linear interpolation processing circuit block is arranged adjacent said initialization arithmetic operation block for linear interpolation operation, wherein the texture processing circuit block is arranged adjacent the linear interpolation operation processing circuit block, and wherein the texture processing circuit block has a block size greater than those of said initialization arithmetic operation circuit block for linear interpolation operation and said linear interpolation processing circuit block.
8. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer wherein the linear interpolation processing circuit block is arranged adjacent said initialization arithmetic operation block for linear interpolation operation, and wherein the initialization arithmetic operation circuit block for linear interpolation operation discriminates through positivenegative discrimination of a linear expression whether or not a noticed point is in an inside of a triangle.
9. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data; and
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive;
wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip, wherein the interpolation processing circuit block includes an initialization arithmetic operation circuit block for linear interpolation operation and a linear interpolation processing block, the initialization arithmetic operation block for linear interpolation operation being arranged adjacent the input buffer, wherein the linear interpolation processing circuit block is arranged adjacent the initialization arithmetic operation block for linear interpolation operation, and wherein the linear interpolation processing circuit block performs processing of pixels within a fixed united range which is set independently of a form of a display memory and independently of a page boundary of the display memory.
10. A graphics plotting apparatus which receives polygon rendering data of apexes of a unit graphic form including three-dimensional coordinates (x, y, z), red, green and blue data, homogeneous coordinates (s, t) of a texture and a homogeneous term q to perform a rendering process, comprising:
a memory block for storing display data and texture data required at least by one graphic form element;
a logic circuit block including an interpolation processing circuit block for interpolating polygon rendering data of the apexes of the unit graphic form to produce interpolation data of pixels positioned in the unit graphic form and a texture processing circuit block for dividing the homogeneous coordinates (s, t) of the texture included in the interpolation data by the homogeneous term q to produce sq and tq, reading out the texture data from the memory block using texture addresses corresponding to sq and tq and performing application processing of the texture data to the surface of the graphic form elements of the display data;
an input buffer provided at an input portion for the polygon rendering data of the interpolation processing circuit block of the logic circuit block and having a capacity for more than one apex of a three-dimensional graphics plotting primitive; and
a first-in first-out buffer disposed on a receiving side of a bus between circuit blocks which are physically separate from each other, a signal for notification that the first-in first-out buffer will be fully occupied soon being transmitted to a data transmitting side of one of the circuit blocks so that stopping of transfer from the data transmitting side circuit block may be performed from the other data receiving side circuit block, wherein the memory block, the logic circuit block and the input buffer are mounted in a mixed state in one semiconductor chip.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An igloo-shaped structure for use as a toy or a portable shelter, comprising:
a plurality of first rectangular blocks, each first rectangular block having a defined length and width, and having a rectangular shaped trough and a rim surrounding the trough, the rim having adjacent each corner of the first rectangular blocks a pin for engaging a fastening plate; and
a plurality of second rectangular blocks, each second rectangular block having a defined length and width less than the length and width of the first rectangular blocks, a rectangular trough, and having a rim surrounding the trough, the rim having at adjacent each corner of the second rectangular blocks a pin for engaging a fastening plate;
a plurality of curved trapezoidal top pieces to form a dome atop the igloo-shaped structure, each curved trapezoidal top piece including a 15 trapezoidal shaped trough, with a rim surrounding the trough, the rim having adjacent each corner of the curved trapezoidal top pieces a pin of engaging a fastening plate; and
a plurality of fastening plates, each fastening plate having a substantially square shape and including an aperture in each of four corners of the fastening plate for capturing or engaging a pin on a rectangular block or a curved trapezoidal top piece;
whereby the first and second rectangular pieces and the trapezoidal top pieces join together with the fastening plates to form an igloo-shaped structure.
2. An igloo-shaped structure according to claim 1, additionally comprising:
a plurality of third rectangular blocks, each third rectangular block having a rectangular trough and a defined length and width less than the length and width of the second rectangular block and a rim surrounding the trough, the rim having at adjacent each corner of the third rectangular blocks a pin of engaging a fastening plate.
3. An igloo-shaped structure in accordance with claim 2, additionally comprising a plurality of fourth rectangular blocks, having a substantially square shape, a pin adjacent each corner of the fourth rectangular blocks, and a substantially square shaped trough in the center of the fourth rectangular blocks and a rim surrounding the trough.
4. An igloo-shaped structure in accordance with claim 2, wherein the blocks are made from transparent or translucent plastic.
5. An igloo-shaped structure in accordance with claim 4, wherein the plastic is substantially rigid.
6. An igloo-shaped structure in accordance with claim 5, wherein the plastic is polyethylene, polypropylene, or polystyrene.
7. An igloo-shaped structure in accordance with claim 2, wherein the fastening plates are made of natural or synthetic rubber.
8. An igloo-shaped structure in accordance with claim 1, wherein the blocks are aluminum or fiberglass.
9. An igloo-shaped structure according to claim 3, wherein the trough slopes inwardly from therein to allow the rim of the blocks to curve as they are stacked.
10. An igloo-shaped structure according to claim 1, wherein the trough slopes inwardly from therein to allow the rim of the blocks to curve as they are stacked.
11. An igloo-shaped structure according to claim 9, wherein each of the first through fourth rectangular blocks have a pair of additional outwardly extending pins approximately midway on an upper edge of the rim and a pair of additional pins on a lower edge of the rim, to allow the blocks to be staggered.
12. An igloo-shaped structure according to claim 11, additionally comprising a plurality of blocks approximately half the length of the first through fourth rectangular block to start a row such that it will stagger the row above or below.