1. An apparatus comprising:
a non-volatile memory circuit configured and arranged for storing electronic data;
a host interface circuit configured and arranged to receive and transmit user data between a host and the non-volatile memory circuit; and
logic circuitry configured and arranged to
generate an error detection code based on user data received from the host,
generate a first set of check bits by combining the error detection code with a hashed data address of the user data, and
write the check bits with the user data in the non-volatile memory circuit.
2. The apparatus of claim 1, wherein the logic circuitry is further configured and arranged to, upon receiving a request to retrieve the user data from the non-volatile memory circuit,
generate a second set of check bits based on the hashed data address and data retrieved from a data storage location identified by a data address, and
validate the data retrieved from the data address based on the first and second sets of check bits.
3. The apparatus of claim 2, wherein the logic circuitry is further configured and arranged to, based upon a failure to validate the data retrieved from the data address, determine an intended address of the user data based on the user data and the check bits associated with the user data and the check bits associated with the user data immediately after the data address.
4. The apparatus of claim 3, wherein the logic circuitry determines a unique logical block address for the user data 99.9977% of the time for a 33-bit wide address based on three sequential sets of user data and check bits.
5. The apparatus of claim 1, wherein the apparatus further includes hash logic circuitry configured and arranged to pseudo-randomly assign a hashed data address for the data address of the user data.
6. The apparatus of claim 5, wherein the hash logic circuitry is further configured and arranged to calculate a hashed value of the hashed data address that is unique for all address numbers that are multiples of a specified power of 2.
7. The apparatus of claim 5, wherein the hash logic circuitry is further configured and arranged to compute a hashed value of the hashed data address using only XOR, NOT, and AND logic gates.
8. The apparatus of claim 5, wherein the hash logic circuitry is further configured and arranged to repeat the hashed data address once every 65,536 logical block addresses.
9. The apparatus of claim 5, wherein the hash logic circuitry is further configured and arranged to prevent the hashed data address from repeating within a logical band of data addresses.
10. The apparatus of claim 1, wherein the logic circuitry is further configured and arranged to determine an intended physical block address of the user data based on the check bits and user data from which a logical block address of the user data is determined.
11. The apparatus of claim 1, wherein the logic circuitry is further configured and arranged to determine, based on the check bits and the user data, a logical block address of the user data.
12. The apparatus of claim 1, wherein the check bits further include a pseudorandom data address based on the address of the user data.
13. The apparatus of claim 1, wherein the number of check bits is less than a bit-width of the data address.
14. The apparatus of claim 1, wherein a bit-length of the check bits is 16-bits and the bit-length of the data address of the user data is 40-bits.
15. The apparatus of claim 1, further comprising a plurality of IOEDC checker circuits between boundaries of subsystems in the apparatus, each IOEDC checker circuit including a set of the logic circuitry and being configured and arranged to, for user data communicated between the subsystems: generate the error detection code, generate the first set of check bits and write the check bits.
16. A method of encodingdecoding electronic data including:
upon receiving a request to write data in a non-volatile memory circuit,
generating a first check bit field, using an error detection code, based on user data received from a host,
combining the first check bit field with a data address of the user data, and
writing the combined first check bit field and user data in the non-volatile memory circuit; and
upon receiving a request to retrieve the user data from the non-volatile memory circuit,
generating a second check bit field based on the data address and data retrieved from a data storage location identified by the address, and
validating the data retrieved from the data address based on the first and second check bit fields.
17. The method of claim 16 further including determining a unique logical block address of the user data.
18. The method of claim 16, wherein the step of validating the data retrieved from the data address based on the first and second check bit fields further includes generating a second check bit field for neighboring user data based on respective data addresses for the neighboring user data and data retrieved from each of the data addresses.
19. The method of claim 16, wherein the step of combining the check bit field with the data address of the user data further includes computing a hashed value of the user data address using only XOR, NOT, and AND logic gates.
20. The method of claim 19, wherein computing the hashed value includes computing the hashed value without propagating arithmetic carry information across a bit width associated with the computation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A shock absorber comprising:
a first pressure tube defining a first working chamber;
a first piston disposed within said first pressure tube, said first piston dividing said first working chamber into an upper working chamber and a lower working chamber;
a piston rod attached to said piston, said piston rod extending through one of said upper and lower working chambers:
a compression hydraulic stop cushioning a full compression movement of said shock absorber.
2. The shock absorber of claim 1, wherein said compression hydraulic stop is disposed outside of said pressure tube.
3. The shock absorber of claim 1, wherein said compression hydraulic stop comprises:
a second pressure tube surrounding said first pressure tube to define a second working chamber; and
a second piston in hydraulic communication with said second working chamber.
4. The shock absorber of claim 3, wherein said second piston is disposed within said second working chamber.
5. The shock absorber of claim 4, wherein said second piston is attached to said second pressure tube.
6. The shock absorber of claim 4, wherein said second piston is attached to said first pressure tube.
7. The shock absorber of claim 3, wherein said second piston is attached to said second pressure tube.
8. The shock absorber of claim 3, wherein said second piston is attached to said first pressure tube.
9. The shock absorber of claim 3, wherein said second pressure tube defines a reduced diameter section within said second working chamber.
10. The shock absorber of claim 9, wherein said second piston is attached to said first pressure tube.
11. The shock absorber of claim 3, wherein said compression hydraulic stop further comprise a reservoir tube defining a hydraulic fluid chamber in communication with said second working chamber.
12. The shock absorber of claim 11, wherein said second piston is disposed within said hydraulic fluid chamber.
13. The shock absorber of claim 11, wherein said second piston is disposed within said second working chamber.
14. The shock absorber of claim 11, wherein said second piston is attached to said second pressure tube.
15. The shock absorber of claim 11, wherein said compression hydraulic stop further comprises a floating piston, said floating piston defining said hydraulic fluid chamber and a pneumatic chamber.
16. The shock absorber of claim 15, wherein said second piston is disposed within said hydraulic fluid chamber.
17. The shock absorber of claim 16, wherein said second piston is disposed within said second working chamber.
18. The shock absorber of claim 16, wherein said second piston is attached to said second pressure tube.