1-15. (canceled)
16. A method of quality control testing a FXIII containing sample which comprises the step of detecting the presence of or measuring the concentration of pre-activated FXIII (FXIIIaO) in said sample.
17. The method as defined in claim 16, wherein the presence of FXIIIaO in said sample is detected by chromatographic separation.
18. The method as defined in claim 17, wherein the chromatographic separation comprises anion exchange HPLC.
19. The method as defined in claim 18, wherein the anion exchange column comprises a DEAE-anion column.
20. The method as defined in claim 19, wherein the DEAE-anion column comprises TSKgel DEAE-NPR.
21. The method as defined in claim 19, wherein an equilibrating buffer and an elution buffer comprise Tris at a concentration ranging from about 20 mM to about 100 mM.
22. The method as defined in claim 21, wherein the equilibrating buffer and the elution buffer are buffered to a pH ranging between about 7 to about 8.
23. The method as defined in claim 16, which comprises the steps of detecting the presence of pre-activated FXIII (FXIIIaO) and measuring the concentration of pre-activated FXIII (FXIIIaO) in said sample.
24. The method as defined in claim 23, wherein the step of measuring the concentration of pre-activated FXIII (FXIIIaO) comprises measuring the activity of FXIII in the presence (activated FXIII) and absence (pre-activated FXIII) of thrombin.
25. A method as defined in claim 24, wherein the step of measuring activatedpre-activated FXIII comprises fluorometric analysis in the presence of a fluorescent or non-fluorescent FXIII substrate.
26. The method as defined in claim 25, wherein the fluorescent substrate comprises Abz-NE(Cad-Dnp)EQVSPLTLLK.
27. The method as defined in claim 23, wherein the concentration of FXIII is measured in the presence of a surfactant.
28. A quality control kit for determining the quality of a Factor XIII (FXIII) containing sample which comprises pre-activated FXIII (FXIIIaO) detecting or measuring components and instructions to use said kit in accordance with the methods as defined in claim 16.
29. The method as defined in claim 16, wherein the measuring of pre-activated FXIII comprises using a fluorescent substrate comprising Abz-NE(Cad-Dnp)EQVSPLTLLK.
30. A method of detecting the presence of pre-activated FXIII (FXIIIaO) which comprises detecting pre-activated FXIII (FXIIIaO) with a chromatographic separation step.
31. A method of measuring the concentration of pre-activated FXIII (FXIIIaO), which comprises measuring the activity of FXIII in the presence and absence of thrombin.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit, comprising:
an input node operable to receive test data;
first circuitry configurable as a first delay circuit that is coupled to the node, operable to generate a first test signal by delaying the test data a first delay time, and operable to generate a second test signal by delaying the test data a second delay time;
second circuitry configurable as a first scan chain that is coupled to the first delay circuit and is operable to receive the first test signal; and
third circuitry configurable as a second scan chain that is coupled to the first delay circuit and is operable to receive the second test signal.
2. The integrated circuit of claim 1 wherein:
the first circuitry is operable to generate a third test signal by delaying the test data a third delay time; and
the integrated circuit further comprises fourth circuitry configurable as a third scan chain that is coupled to the first delay circuit and is operable to receive the third test signal.
3. The integrated circuit of claim 1 wherein the first delay circuit further comprises at least one delay element configurable to set the duration of the first delay time.
4. The integrated circuit of claim 1 wherein the first delay circuit further comprises at least one multiplexer configurable to provide the first test signal to the third circuitry and the second test signal to the second circuitry.
5. The integrated circuit of claim 4 wherein the at least one multiplexer is programmable.
6. The integrated circuit of claim 1 wherein the first circuitry further comprises at least one synchronizer operable to synchronize the test data with a clock.
7. The integrated circuit of claim 1, further comprising:
fourth circuitry configurable as a second delay circuit that is coupled to at least one of the second and third circuitry, operable to generate a third test signal by delaying the test data a third delay time; and
fifth circuitry configurable as a third scan chain that is coupled to the second delay circuit and is operable to receive the third test signal.
8. The integrated circuit of claim 1, further comprising an output node operable to receive test data propagated through the first and second scan chains; and
wherein the input node comprises a pin.
9. The integrated circuit of claim 1, further comprising first and second output nodes operable to receive test data propagated through the first and second scan chains; and
wherein the input node comprises a pin.
10. The integrated circuit of claim 1, further comprising a logic circuit coupled to the first and second scan chains and generating a serial data stream; and
wherein the input node comprises a pin.
11. A testing system, comprising:
an interface operable to provide test data to an input node of an integrated circuit; and
a programmer operable to program first circuitry of the integrated circuit to generate a first test signal by delaying the test data a first delay time, and to generate a second test signal by delaying the test data a second delay time, the programmer further operable to configure second circuitry of the integrated circuit as a first scan chain to receive the first test signal, and to configure third circuitry of the integrated circuit as a second scan chain to receive the second test signal.
12. A method, comprising:
generating a first test signal by delaying test data a first delay time;
generating a second test signal by delaying the test data a second delay time;
providing the first test signal to a first scan chain; and
providing the second test signal to a second scan chain.
13. The method of claim 12 wherein:
generating the first and second test signals comprises configuring first circuitry as a delay circuit;
providing the first test signal comprises configuring second circuitry as the first scan chain; and
providing the second test signal comprises configuring third circuitry as the second scan chain.
14. The method of claim 13 wherein a tester configures the first, second and third circuitry.