What is claimed is:
1. A filter element comprising:
a first filter layer formed of a non-woven fabric;
a second filter layer formed of an open-pore foam attached to said first filter layer; and,
said non-woven fabric being a felt strengthened by an impregnation of a curing liquid to cause said first filter layer to function as a carrier imparting stiffness to said filter element.
2. The filter element of claim 1, wherein said felt defines a form stable body which is essentially rigid.
3. The filter element of claim 1, wherein said liquid is a chemically curing liquid.
4. The filter element of claim 1, wherein said liquid is a thermally curing liquid.
5. The filter element of claim 1, wherein said liquid is a chemically and thermally curing liquid.
6. The filter element of claim 1, wherein said liquid is a resin.
7. The filter element of claim 6, wherein said resin is a phenol resin.
8. The filter element of claim 1, wherein said open-pore foam is attached to the cured felt with adhesive.
9. The filter element of claim 8, wherein said adhesive is a two-component adhesive.
10. The filter element of claim 8, wherein said adhesive is in the form of a powder application.
11. The filter element of claim 8, wherein the adhesive application is in the form of a lattice.
12. The filter element of claim 11, wherein said lattice is a uniform lattice.
13. The filter element of claim 1, wherein the form-stable felt has a side facing away from said open-pore foam; and, wherein said filter element further comprises a fine-filter layer arranged on said side; and, said fine-filter layer is in the form of a thin fine fiber felt layer.
14. The filter element of claim 1, wherein said filter element is washable.
15. The filter element of claim 1, wherein filter element has corners perpendicular to said filter layers thereof; and, said corners are rounded in the peripheral direction of said filter element.
16. The filter element of claim 1, wherein said open-pore foam is thermally welded to said felt.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A flip-flop implemented in a programmable integrated circuit (IC), comprising:
a dual-output lookup table (LUT) having first and second output terminals, the LUT being programmed to implement as a first function a master latch driving the first output terminal, the LUT being further programmed to implement as a second function a slave latch driving the second output terminal, wherein:
a first input terminal of the LUT drives the first and second functions and is coupled to the first output terminal of the LUT;
a second input terminal of the LUT drives the second function and is coupled to the second output terminal of the LUT; and
a third input terminal of the LUT drives the first and second functions and is coupled to provide a clock signal to the flip-flop.
2. The flip-flop of claim 1, wherein the LUT comprises a 6-input LUT.
3. The flip-flop of claim 1, wherein the first input terminal of the LUT is coupled to the first output terminal of the LUT, and the second input terminal of the LUT is coupled to the second output terminal of the LUT, through a programmable interconnect structure of the programmable IC.
4. The flip-flop of claim 1, wherein a fourth input terminal of the LUT drives the first function and is coupled to provide a data input for the master latch.
5. The flip-flop of claim 1, wherein:
the LUT is further programmed to implement a third function of two data input signals, the third function providing a data input for the master latch; and
fourth and fifth input terminals of the LUT drive the third function and are coupled to provide the two data input signals to the LUT.
6. A method of implementing a flip-flop in a programmable integrated circuit (IC) comprising dual-output lookup tables (LUTs) and interconnect, the method comprising:
programming one of the LUTs to implement a master latch with an output of the master latch being provided as a first output of the LUT;
programming the LUT to implement a slave latch with an output of the slave latch being provided as a second output of the LUT;
programming the interconnect to provide the first output of the LUT as an input signal to the master latch and to the slave latch;
programming the interconnect to provide the second output of the LUT as an input signal to the slave latch; and
programming the interconnect to provide a clock signal as an input signal to the master latch and the slave latch.
7. The method of claim 6, further comprising:
programming the interconnect to provide a data input signal to the master latch.
8. The method of claim 6, further comprising:
programming the LUT to implement a function of two input signals, the function providing a data input signal to the master latch; and
programming the interconnect to provide the two input signals to the LUT.
9. The method of claim 6, further comprising:
programming the LUT to select a dual-output mode for the LUT.
10. The method of claim 6, wherein the programmable IC comprises a programmable logic device (PLD).
11. The method of claim 9, wherein the PLD comprises a field programmable gate array (FPGA).
12. A programmable integrated circuit (IC), comprising:
a dual-output lookup table (LUT) programmed to implement a master latch and a slave latch, with an output of the master latch being provided at a first output terminal of the LUT and an output of the slave latch being provided at a second output terminal of the LUT;
means for programmably coupling the first output terminal of the LUT to a first input terminal of the LUT;
means for programmably coupling the second output terminal of the LUT to a second input terminal of the LUT; and
means for programmably coupling a clock input signal to a third input terminal of the LUT.
13. The programmable IC of claim 12, wherein the LUT comprises a 6-input LUT.
14. The programmable IC of claim 12, wherein the means for programmably coupling the first output terminal of the LUT to the first input terminal of the LUT, and the means for programmably coupling the second output terminal of the LUT to the second input terminal of the LUT, comprises a programmable interconnect structure coupled to the LUT.
15. The programmable IC of claim 12, wherein the LUT comprises a fourth input terminal coupled to provide a data input signal for the master latch.
16. The programmable IC of claim 12, wherein:
the LUT is further programmed to implement a function of two data input signals, the function providing a data input for the master latch; and
the programmable IC further comprises means for programmably coupling the two data input signals to the LUT.
17. The programmable IC of claim 12, wherein the programmable IC comprises a programmable logic device (PLD).
18. The programmable IC of claim 17, wherein the PLD comprises a field programmable gate array (FPGA).