1. Secondary electrochemical generator, with an alkaline electrolyte, containing a non-sintered electrode comprising a two-dimensional conductive support covered by a layer containing an electrochemically active material and a binder, characterized in that the said binder is a mixture of a cellulose compound and a styrene-acrylate copolymer of general formula:
(CH2CHC6H5)P(CH2CHCOOR)qx.
2. Generator according to claim 1, in which the proportion of the said styrene-acrylate copolymer is less than 4% by weight of the said layer.
3. Generator according to claim 2, in which the proportion of the said styrene-acrylate copolymer is between 0.15% and 3% by weight of the said layer.
4. Generator according to claim 1, in which the said cellulose compound is chosen from methylcellulose, carboxymethylcellulose, hydroxypropylmethyl-cellulose, hydroxypropylcellulose and hydroxyethylcellulose.
5. Generator according to claim 1, in which the proportion of the said cellulose compound is comprised between 0.1 and 1% by weight of the said layer.
6. Generator according to claim 1, in which the said electrochemically active material comprises a nickel hydroxide.
7. Generator according to claim 6, in which the said nickel hydroxide also contains at least one syncrystallized hydroxide of an element chosen from zinc, cadmium and magnesium and at least one syncrystallized hydroxide of an element chosen from cobalt, manganese, aluminium, yttrium, calcium, strontium, zirconium, copper.
8. Generator according to claim 6, in which the said nickel hydroxide has a spheroidal shape and has a grain size comprised between 7 m and 20 microns.
9. Generator according to claim 1, in which the said layer also comprises a conductive material consisting principally of a compound of cobalt.
10. Generator according to claim 9, in which the said compound of cobalt is chosen from cobalt metal Co, cobalt oxide CoO, cobalt hydroxide Co(OH)2, the mixed oxide of lithium and cobalt LiCoO2 and an oxide of conductive cobalt oxide of a valency greater than 2.
11. Generator according to claim 1, in which the said layer also contains at least one other compound chosen from the compounds of zinc, yttrium, ytterbium and calcium.
12. Generator according to claim 11, in which the said compound is a compound of yttrium.
13. Generator according to claim 12, in which the said compound of yttrium is chosen from yttrium oxide Y2O3 and yttrium hydroxide Y(OH)3.
14. Generator according to claim 11, in which the said compound is a compound of ytterbium.
15. Generator according to claim 14, in which the said compound of ytterbium is chosen from ytterbium oxide Yb2O3 and ytterbium hydroxide Yb(OH)3.
16. Generator according to claim 1, in which the said layer also contains polymer fibres.
17. Generator according to claim 1, in which the said two-dimensional conductive support is chosen from a solid or perforated strip, an expanded metal, a grid and a fabric.
18. Generator according to claim 1, also comprising a metal-hydride negative electrode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of fabricating an integrated circuit, comprising the steps of:
depositing material to form a layer using a low AC bias power;
depositing additional material to said layer using a high AC bias power; and
depositing additional material to said layer using a lower AC bias power, wherein said high AC bias power is higher than both said low AC bias power and said lower AC bias power.
2. The method of claim 1, wherein said material comprises copper.
3. The method of claim 1, wherein said material comprises a copper alloy.
4. The method of claim 1, wherein said low AC bias power is in the range of 0 W to 600 W.
5. The method of claim 1, wherein said low AC bias power is in the range of 0 W to 400 W.
6. The method of claim 1, wherein said high AC bias power is in the range of 300 W to 1200 W.
7. The method of claim 1, wherein said high AC bias power is in the range of 600 W to 1000 W.
8. The method of claim 1, wherein said lower AC bias power is in the range of 0 W to 300 W.
9. The method of claim 1, wherein said lower AC bias power is 0 W.
10. The method of claim 1, wherein said step of depositing with said low AC bias power occurs prior to said step of depositing with said high AC bias power.
11. The method of claim 1, wherein said step of depositing with said low AC bias power occurs after said step of depositing with said high AC bias power.
12. A method of fabricating an integrated circuit comprising the steps of:
forming a dielectric layer over a semiconductor body;
forming a hole in said dielectric layer;
depositing a barrier layer over said dielectric layer including in said hole;
depositing a seed layer over said barrier layer using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower AC bias power step, wherein said high AC bias power step is higher than both said low AC bias power step and said lower AC bias power step; and
filling said hole with a metal using an electrochemical deposition process.
13. The method of claim 12, wherein said seed layer comprises copper.
14. The method of claim 12, wherein said seed layer comprises a copper alloy.
15. The method of claim 12, wherein said low AC bias power is in the range of 0 W to 400 W.
16. The method of claim 12, wherein said high AC bias power is in the range of 600 W to 1000 W.
17. The method of claim 12, wherein said lower AC bias power is 0 W.
18. The method of claim 12, wherein said low AC bias power step occurs prior to said high AC bias power step.
19. The method of claim 12, wherein said low AC bias power step occurs after said high AC bias power step.
20. A method of fabricating an integrated circuit comprising the steps of:
forming a dielectric layer over a semiconductor body;
forming a via in said dielectric layer;
forming a trench in said dielectric layer;
depositing a barrier layer over said dielectric layer including in said trench and said via;
depositing a first portion of a seed layer over said barrier layer using a low AC bias power;
depositing a second portion of said seed layer using a high AC bias power;
depositing a third portion of said seed layer using a lower AC bias power, wherein said high AC bias power is higher than both said low AC bias power and said lower AC bias power; and
filling said hole with a metal using an electrochemical deposition process.
21. The method of claim 20, wherein said seed layer comprises copper.
22. The method of claim 20, wherein said seed layer comprises a copper alloy.
23. The method of claim 20, wherein said low AC bias power is in the range of 0 W to 400 W.
24. The method of claim 20, wherein said high AC bias power is in the range of 600 W to 1000 W.
25. The method of claim 20, wherein said lower AC bias power is 0 W.
26. The method of claim 20, wherein said seed layer has a final thickness and said first portion is 20% to 70% of said final thickness.
27. The method of claim 20, wherein said seed layer has a final thickness and said first portion is 50% to 60% of said final thickness.
28. The method of claim 20, wherein said seed layer has a final thickness and said second portion is 20% to 70% of said final thickness.
29. The method of claim 20, wherein said seed layer has a final thickness and said second portion is 30% to 40% of said final thickness.
30. The method of claim 20, wherein said seed layer has a final thickness and said first portion is 1% to 30% of said final thickness.
31. The method of claim 20, wherein said seed layer has a final thickness and said first portion is 10% to 20% of said final thickness.