I claim:
1. A supported noble metal hydrodechlorination catalyst wherein the noble metal, which is in the zero valent state, predominantly resides adjacent the surface of the support and wherein a predominant amount of the noble metal therein is visible under a microscope having a resolution of about 5 and is in the particle size range of from about 30 to about 200 .
2. A catalyst as claimed in claim 1 wherein the support is an oxidic support.
3. A catalyst as claimed in claim 1 wherein the noble metal is a Group VIII noble metal.
4. A catalyst as claimed in claim 1 wherein the noble metal is selected from the group consisting of platinum and palladium.
5. A catalyst as claimed in claim 1 wherein the support is an oxidic support, and the noble metal is selected from the group consisting of platinum and palladium.
6. A catalyst as claimed in claim 1 wherein the support is a pelletized oxidic support, and the noble metal is selected from the group consisting of platinum and palladium.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system, comprising:
a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die;
at least one non-transitory machine readable storage medium, including a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool, wherein the second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports;
a processor-implemented first verification module for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.
2. The system of claim 1, wherein the first verification module includes a first parser module that receives the first and second gate level descriptions of the first and second IC dies and generates a source parsing tree having respective leaves representing each port of the first and second IC dies according to the first gate level description, and a target parsing tree having respective leaves representing each port of the first and second IC dies according to the second gate level description, wherein the first verification module compares each leaf of the target parsing tree to a corresponding leaf of the source parsing tree.
3. The system of claim 2, wherein the first parser module generates:
a source connection list based on the first gate level description, the source connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port; and
a target connection list based on the second gate level description, the target connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port.
4. The system of claim 2, wherein the first parser module generates and stores the following parameters in leaves of the source parsing tree:
for each port of the first die or second die identified as a source port of a connection in the source connection list, a corresponding source list destination die and source list destination port;
for each port of the first die or second die identified as a destination port of a connection in the source connection list, a corresponding source list source die and source list source port; and wherein the first parser module generates and stores the following parameters in leaves of the target parsing tree:
for each port of the first die or second die identified as a source port of a connection in the target connection list, a corresponding target list destination die and target list destination port; and
for each port of the first die or second die identified as a destination port of a connection in the target connection list, a corresponding target list source die and target list source port.
5. The system of claim 4, wherein the first parser module generates:
a source connection list based on the first gate level description, the source connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port; and
a target connection list based on the second gate level description, the target connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port; and
wherein the first verification module further comprises a compare module that generates and outputs the error report if, for a given leaf of the source parsing tree:
the target list source die of the corresponding leaf of the target parsing tree is different from the source list source die of the given leaf,
the target list source port of the corresponding leaf of the target parsing tree is different from the source list source port of the given leaf,
the target list destination die of the corresponding leaf of the target parsing tree is different from the source list destination die of the given leaf, or
the target list destination port of the corresponding leaf of the target parsing tree is different from the source list destination port of the given leaf.
6. The system of claim 5, further comprising a correction module that corrects an error in at least one of the group consisting of the target list source die, target list source port, target list destination port, and the target list destination die if the compare module generates an error report.
7. The system of claim 1, wherein:
the at least one storage medium includes a third portion for storing the verified second gate level description;
the at least one storage medium includes a fourth portion for storing a first microbump mapping data received from the processor implemented tool, the first microbump mapping data identifying connections between ports of the first die and ports of the second die, the first microbump mapping data having a different format from the verified second gate level description; and
the system further comprises a second verification module for comparing the first microbump mapping data to the verified second gate level description and outputting an error report if the first microbump mapping data has an error, the second verification module outputting verified microbump mapping data.
8. The system of claim 7, wherein the second verification module includes a second parser module that receives the verified second gate level description and the first microbump mapping data and generates a source parsing tree having respective leaves representing each port of the first and second IC dies according to the verified second gate level description, and a target parsing tree having respective leaves representing each port of the first and second IC dies according to the microbump mapping data, wherein the second verification module compares each leaf of the target parsing tree to a corresponding leaf of the source parsing tree.
9. The system of claim 8, wherein the second parser module generates:
a source connection list based on the verified second gate level description, the source connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port; and
a target connection list based on the microbump mapping data, the target connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port.
10. The system of claim 8, wherein the second parser module generates and stores the following parameters in leaves of the source parsing tree:
for each port of the first die or second die identified as a source port of a connection in the source connection list, a corresponding source list destination die and source list destination port;
for each port of the first die or second die identified as a destination port of a connection in the source connection list, a corresponding source list source die and source list source port; and wherein the first parser module generates and stores the following parameters in leaves of the target parsing tree:
for each port of the first die or second die identified as a source port of a connection in the target connection list, a corresponding target list destination die and target list destination port; and
for each port of the first die or second die identified as a destination port of a connection in the target connection list, a corresponding target list source die and target list source port.
11. The system of claim 10, wherein the second parser module generates:
a source connection list based on the verified second gate level description, the source connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port; and
a target connection list based on the microbump mapping data, the target connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port; and
wherein the second verification module further comprises a compare module that generates and outputs the error report if, for a given leaf of the source parsing tree:
the target list source die of the corresponding leaf of the target parsing tree is different from the source list source die of the given leaf,
the target list source port of the corresponding leaf of the target parsing tree is different from the source list source port of the given leaf,
the target list destination die of the corresponding leaf of the target parsing tree is different from the source list destination die of the given leaf, or
the target list destination port of the corresponding leaf of the target parsing tree is different from the source list destination port of the given leaf.
12. The system of claim 11, further comprising a correction module that corrects an error in at least one of the group consisting of the target list source die, target list source port, target list destination port, and the target list destination die if the compare module generates an error report.
13. The system of claim 7, wherein:
the at least one storage medium includes a fifth portion for storing a translated microbump mapping data received from a translation tool, the translated microbump mapping data identifying connections between the ports of the first die and the ports of the second die, the translated microbump mapping data having a different format from the first microbump mapping data and from the verified second gate level description; and
the system further comprises a third verification module for comparing the translated microbump mapping data to the verified second gate level description and determining whether the translated microbump mapping data has an error, the third verification module outputting verified translated microbump mapping data.
14. A method, comprising:
providing a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, wherein the first gate level description does not include power or ground ports of the IC dies;
using a computer implemented tool to generate a second gate level description of the first and second circuit patterns, wherein the second gate level description includes power and ground ports of the IC dies;
comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns if the second gate level description has no error.
15. The method of claim 14, further comprising:
generating a microbump mapping data using the computer implemented tool, the microbump mapping data identifying connections between ports of the first die and ports of the second die, the microbump mapping data having a different format from the verified second gate level description;
comparing the microbump mapping data to the verified second gate level description and outputting a verified microbump mapping data if the microbump mapping data has no error; and
performing inter-die layout-versus-schematic verification based on the verified second gate level description and the verified microbump mapping data.
16. A system comprising:
at least one non-transitory machine readable storage medium, including a portion for storing a verified gate level description of a first IC die and a second IC die,
a processor-implemented tool configured to access the verified gate level description of the first and second IC dies, and for generating a first microbump mapping data identifying connections between ports of the first IC die and ports of the second IC die, the first microbump mapping data having a different format from the verified gate level description; and
a verification module for comparing the first microbump mapping data to the verified second gate level description and outputting an error report if the first microbump mapping data has an error, the second verification module outputting verified microbump mapping data.
17. The system of claim 16, wherein the verification module comprises
a first parser module that receives the verified gate level descriptions of the first and second IC dies and generates a source parsing tree having respective leaves representing each port of the first and second IC dies according to the verified gate level descriptions, and a target parsing tree having respective leaves representing each port of the first and second IC dies according to the first microbump mapping data, wherein the verification module compares each leaf of the target parsing tree to a corresponding leaf of the source parsing tree.
18. The system of claim 17, wherein the verification module generates:
a source connection list based on the verified gate level description, the source connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port; and
a target connection list based on the first microbump mapping data, the target connection list including, for each connection between the first IC die and the second IC die, a source die, a destination die, a source port, and a destination port.
19. The system of claim 17, wherein the verification module further comprises a compare module that generates and outputs the error report if, for a given leaf of the source parsing tree:
a target list source die of a corresponding leaf of the target parsing tree is different from a source list source die of the given leaf,
a target list source port of a corresponding leaf of the target parsing tree is different from a source list source port of the given leaf,
a target list destination die of a corresponding leaf of the target parsing tree is different from a source list destination die of the given leaf, or
a target list destination port of a corresponding leaf of the target parsing tree is different from a source list destination port of the given leaf.
20. The system of claim 19, further comprising a correction module that corrects an error in at least one of the group consisting of the target list source die, target list source port, target list destination port, and the target list destination die if the compare module generates an error report.