1. An integrated circuit comprising a plurality of transistors that store a codeword determined by a difference in mobility between a first transistor and a further transistor of the plurality of transistors, wherein the plurality of transistors are arranged to form a bi-stable circuit having two stable states; and wherein the difference in mobility between the first transistor and the further transistor biases the bi-stable circuit towards one or the other of the stable states to determine the codeword.
2. The integrated circuit of claim 1, wherein the plurality of transistors comprise a first branch of series connected transistors comprising the first transistor, and a second branch of series connected transistors comprising the further transistor; wherein an output node of the first branch is connected to an input node of the second branch, and wherein an output node of the second branch is connected to an input node of the first branch, thereby forming the bi-stable circuit.
3. The integrated circuit of claim 1, comprising a plurality of the bi-stable circuits.
4. The integrated circuit of claim 1, wherein at least the first transistor has a width to length ratio of less than one.
5. The integrated circuit of claim 1, wherein at least the first transistor is located at a predetermined location of the die of the integrated circuit, the predetermined location being more susceptible to undergo physical stress than other areas of the die.
6. The integrated circuit of claim 5, wherein the predetermined location is at a corner or an edge of the die of the integrated circuit.
7. The integrated circuit of claim 1 wherein a stress layer (CAP) is provided to influence the stress within the transistors, thereby controlling the mobilities of the transistors and hence the value of the codeword.
8. The integrated circuit of claim 7, wherein the stress layer comprises a compressive stress layer and a tensile stress layer, the compressive stress layer setting a first level of mobility and the tensile stress layer setting a second level of mobility.
9. Apparatus comprising the integrated circuit of claim 1 and a reader for connecting to the integrated circuit and reading the codeword, the reader comprising a driver for driving the integrated circuit to determine the codeword.
10. A method for reading a codeword stored in an integrated circuit according to claim 1, the method comprising driving the integrated circuit to determine a codeword, the codeword being determined by the difference in mobility between the first transistor and a further transistor of a bi-stable circuit of the integrated circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A dynamic voltage scaling system based on on-chip monitoring and voltage prediction, comprising:
a main circuit that has integrated on-chip monitoring circuits,
a supply voltage scaling module, and
a voltage converter connected to an output terminal of the supply voltage scaling module, with an output terminal of the voltage converter connected to an input terminal of the main circuit, wherein, the supply voltage scaling module comprises
a state transition probability generation module and an error prediction module designed according to the main circuit, and a sampling and statistics module and a state recording module connected in sequence to the output terminals of the on-chip monitoring circuits, the output terminals of the state recording module and state transition probability generation module are connected to the input terminals of the error prediction module; wherein the on-chip monitoring circuits create monitored error signals and sends the monitored error signals to the sampling and statistics module which calculates the error rate of the main circuit in the current time slice, and outputs to the state recording module, and the state recording module records the error rate and the corresponding supply voltage; the error prediction module utilizes the Markov theory to predict the error rate of the main circuit in a future time slice according to the probability generated by the state recording module and the state transition probability generation module, and generate regulation signals to control the output voltage of the voltage converter.
2. The dynamic voltage scaling system based on on-chip monitoring and voltage prediction according to claim 1, wherein, the state transition probability generation module employs a state transition probability look-up table.
3. The dynamic voltage scaling system based on on-chip monitoring and voltage prediction according to claim 2, wherein, the state transition probability look-up table is created as follows: after the main circuit is designed completely, the main circuit is subjected to run a large-size program at different voltages, and perform statistics in a large quantity, to obtain the state transition probability of the main circuit from the current state skip to the next state at different voltages, and store in the form of a look-up table.
4. The dynamic voltage scaling system based on on-chip monitoring and voltage prediction according to claim 1, wherein, the processing procedure of the sampling and statistics module comprises the following steps: first, dividing the operation time of the main circuit into N time slices in equal size; next, performing statistics on the total number of error signals Nerror in the main circuit sent from the on-chip monitoring circuits in n\u22121th time slice; finally, calculating the error rate Rerror of the main circuit in the n\u22121th time slice: Rerror=NerrorNtotal, where, Ntotal is the total number of sampled signals of the main circuit in the n\u22121th time slice; wherein, 2\u2266n\u2266N\u22121, N\u22673, and both N and n are integral number.
5. The dynamic voltage scaling system based on on-chip monitoring and voltage prediction according to claim 4, wherein, the length of the time slice is not shorter than the maximum duration required for performing voltage scaling once by the voltage converter.