1. A level shifter, comprising:
an input voltage supply node and an input reference node operative within a first power domain;
an output voltage supply node and an output reference node operative within a second power domain;
an input signal node for receiving an input signal operable within said first power domain;
an output signal node;
a level shifter network which is configured to receive said input signal at said input signal node, to perform voltage shifting between said input voltage supply node and said output voltage supply node and between said input reference node and said output reference node, and to provide an output signal via said output signal node, wherein said output signal represents said input signal and is operable within said second power domain; and
wherein said level shifter circuit further comprises a ground bypass input for receiving a ground bypass signal, and wherein said level shifter circuit bypasses at least a portion of said level shifter circuit performing voltage shifting between said input reference node and said output reference node when said ground bypass signal indicates ground bypass.
2. The level shifter of claim 1, wherein said level shifter network further comprises a voltage supply bypass input configured to receive a voltage supply bypass signal, and wherein said level shifter network bypasses at least a portion of the level network performing voltage shifting between said input voltage supply node and said output voltage supply node when said voltage supply bypass signal indicates voltage supply bypass.
3. The level shifter of claim 1, wherein said level shifter network further comprises an isolation input configured to receive an isolation signal, and wherein said level shifter network drives said output node to one of said output voltage supply node and said output reference node when said isolation signal indicates isolation.
4. The level shifter of claim 1, wherein said level shifter network comprises:
a reference level shifter which receives said input signal and which provides a corresponding intermediate signal operable between said input voltage supply node and said output reference node; and
a power level shifter which receives said intermediate signal and which provides said output signal operable between said output voltage supply node and said output reference node.
5. The level shifter of claim 4, wherein said reference level shifter comprises:
a first inverter coupled between said input voltage supply node and said input reference node having an input receiving said input signal and an output providing an inverted input signal operative within said first power domain;
a second inverter coupled between said input voltage supply node and a first node, said second inverter having an input receiving said input signal and an output coupled to a first intermediate node;
a third inverter coupled between said input voltage supply node and a second node, said third inverter having an input receiving said inverted input signal and an output coupled to a second intermediate node;
a first level shift device having a current path coupled between said first node and said output reference node and having a control input coupled to said second intermediate node; and
a second level shift device having a current path coupled between said second node and said output reference node and having a control input coupled to said first intermediate node.
6. The level shifter of claim 5, wherein said first, second and third inverters each comprise complementary metal-oxide semiconductor inverters and wherein said first and second level shift devices each comprise an N-channel metal-oxide semiconductor device.
7. The level shifter of claim 5, further comprising a bypass circuit which, when asserted for ground voltage shifting bypass, couples said first node to said output reference node and decouples said first level shift device from said output reference node.
8. The level shifter of claim 4, wherein said reference level shifter provides said intermediate signal and an inverted intermediate signal, and wherein said power level shifter comprises:
a first inverter coupled between said output reference node and a first node, said first inverter having an input receiving said inverted intermediate signal and an output coupled to an intermediate output node;
a second inverter coupled between said output reference node and a second node, said second inverter having an input receiving said intermediate signal and an output coupled to a third node;
a first level shift device having a current path coupled between said first node and said output voltage supply node and having a control input coupled to said third node;
a second level shift device having a current path coupled between said second node and said output voltage supply node and having a control input coupled to said intermediate output node; and
a buffer having an input coupled to said intermediate output node and an output coupled to said output signal node providing said output signal.
9. The level shifter of claim 8, wherein said first and second inverters each comprise complementary metal-oxide semiconductor inverters and wherein said first and second level shift devices each comprise a P-channel metal-oxide semiconductor device.
10. The level shifter of claim 8, further comprising a bypass circuit which, when asserted for power shifting bypass, couples said first node to said output voltage supply node.
11. The level shifter of claim 8, further comprising an isolation circuit which, when asserted for isolation, drives said intermediate output node to one of said output voltage supply node and said output reference node.
12. A method of voltage level shifting a binary signal between independent voltage domains, comprising:
receiving an input binary signal operative within a first power domain, wherein the input binary signal switches between a first reference voltage and a first source voltage;
level shifting the input binary signal to an output binary signal operative within a second power domain, wherein the output binary signal switches between a second reference voltage and a second source voltage, and wherein the second reference voltage is different from the first reference voltage and the second source voltage is different from the first source voltage;
receiving a reference bypass signal indicating that the first and second reference voltages are at a common voltage level; and
bypassing said level shifting between the first and second reference voltages when the bypass signal indicates that the first and second reference voltages are at a common voltage level.
13. The method of claim 12, wherein said level shifting comprises:
level shifting the first reference voltage of the input binary signal to the second reference voltage and providing an intermediate binary signal which switches between the second reference voltage and the first source voltage; and
level shifting the first source voltage of the intermediate signal to the second source voltage and providing the output binary signal which switches between the second reference voltage and the second source voltage of the second power domain.
14. The method of claim 12, further comprising:
receiving a voltage supply bypass signal indicatin that the first and second source voltages are at a common voltage level; and
bypassing said level shifting between the first and second source voltages when the voltage supply bypass signal indicates that the first and second source voltages are at a common voltage level.
15. The method of claim 12, further comprising:
receiving an isolation signal indicating a lower power state; and
asserting the output binary signal to one of the second reference voltage and the second source voltage during the low power state.
16. A level shifter, comprising:
an input voltage supply node and an input reference node operative within a first power domain;
an output voltage supply node and an output reference node operative within a second power domain;
an input signal node for receiving an input signal operable within said first power domain;
an output signal node;
a level shifter circuit which is configured to receive said input signal at said input signal node, to perform voltage shifting between said input voltage supply node and said output voltage supply node and between said input reference node and said output reference node, and to provide an output signal via said output signal node, wherein said output signal represents said input signal and is operable within said second power domain; and
wherein said level shifter circuit further comprises a voltage supply bypass input for receiving a voltage supply bypass signal, and wherein said level shifter circuit bypasses at least a portion of said level shifter circuit performing voltage shifting between said input voltage supply node and said output voltage supply node when said voltage supply bypass signal indicates voltage supply bypass.
17. The level shifter of claim 16, wherein said level shifter circuit further comprises an isolation input configured to receive an isolation signal, and wherein said level shifter circuit drives said output node to one of said output voltage supply node and said output reference node when said isolation signal indicates isolation.
18. A method of voltage level shifting a binary signal between independent voltage domains, comprising:
receiving an input binary signal operative within a first power domain, wherein the input binary signal switches between a first reference voltage and a first source voltage;
level shifting the input binary signal to an output binary signal operative within a second power domain, wherein the output binary signal switches between a second reference voltage and a second source voltage, and wherein the second reference voltage is different from the first reference voltage and the second source voltage is different from the first source voltage;
receiving a source bypass signal indicating that the first and second source voltages are at a common voltage level; and
bypassing said level shifting between the first and second source voltages when the bypass signal indicates that the first and second source voltages are at a common voltage level.
19. The method of claim 18, further comprising:
receiving an isolation signal indicating a lower power state; and
asserting the output binary signal to one of the second reference voltage and the second source voltage during the low power state.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a plurality of lines disposed on a semiconductor substrate; and
remaining line patterns disposed spaced apart from the lines on extensions from the lines,
wherein the lines include first end-portions adjacent to the remaining line patterns,
the remaining line patterns include second end-portions adjacent to the lines, and
the first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.
2. The semiconductor device as claimed in claim 1, wherein each of the first end-portions has a width greater than the lines.
3. The semiconductor device as claimed in claim 1, wherein a sidewall slope of the first end-portions is more gentle than a sidewall slope of the lines.
4. The semiconductor device as claimed in claim 1, further comprising a device isolation layer disposed on the substrate to define a dummy active region and a cell active region,
wherein the dummy active region is between the first end-portions and the second end-portions.
5. The semiconductor device as claimed in claim 4, wherein a width of the dummy active region is greater than that of the cell active region.
6. The semiconductor device as claimed in claim 4, further comprising:
dummy floating gates disposed between the lines and the dummy active region; and
cell floating gates disposed between the lines and the cell active region.
7. The semiconductor device as claimed in claim 6, wherein:
at least some of adjacent ones of the dummy floating gates are in contact with each other, and
all of the cell floating gates are spaced apart from each other.
8. The semiconductor device as claimed in claim 1, wherein the remaining line patterns are spaced apart from each other.
9. The semiconductor device as claimed in claim 8, wherein:
the remaining line patterns further include third end-portions spaced apart from the second end-portions, and
widths of the second and third end-portions are greater than widths of the lines.
10. The semiconductor device of claim 1, wherein at least portions of the remaining line patterns are connected to each other.
11.-20. (canceled)