1. A method for classification of vehicles comprising:
(a) calibrating a transformation angle between a camera image and a road surface;
(b) detecting moving objects on the road surface in the camera image;
(c) establishing a vertical axis of symmetry for each of the moving objects;
(d) detecting dominant horizontal edges intersecting with the vertical axis of symmetry for each of the moving objects;
(e) tracking the dominant horizontal edges for a plurality of consecutive video frames;
(f) projecting each of the dominant horizontal edges onto a ground plane;
(g) treating each pair of adjacent projected edges as a projected surface;
(h) calculating changes in the projected surface; and
(i) calculating distinct structural signatures from the changes in the projected surfaces.
2. The method of claim 1, further comprising:
classifying the distinct structural signatures in a class based on the distinct structural signatures and wherein the moving object is a motor vehicle and the class includes one of the following: sedan, pickup, minivan and sport utility vehicle (SUV).
3. The method of claim 2, comprising:
separating asymmetric parts of the moving objects and classifying them as non-vehicles, and after separating asymmetric parts of the moving objects and classifying them as non-vehicles, projecting a lower edge of the blob onto the road surface using the transformation in classification step (a), and wherein the projected size is a width of the vehicle.
4. The method of claim 1, further comprising after treating each pair of adjacent projected edges as a projected surface, calculating a speed of a vehicle using a location of a lowest projected surface at at least two different times.
5. The method of claim 2, further comprising classifying passenger vehicles on a road surface.
6. The method of claim 2, further comprising allocating parking garage andor parking lot spaces based on a vehicle classification.
7. The method of claim 2, further comprising calculating vehicle speed for law enforcement.
8. The method of claim 2, further comprising ensuring limited andor controlled access to vehicles for security related applications.
9. A system for classification of vehicles comprising:
a camera for capturing images of at least one moving object; and
a computer processing unit, which performs the following steps:
(a) calibrating a transformation angle between a camera image and a road surface;
(b) detecting moving objects on the road surface in the camera image;
(c) establishing a vertical axis of symmetry for each of the moving objects;
(d) detecting dominant horizontal edges intersecting with the vertical axis of symmetry for each of the moving objects;
(e) tracking the dominant horizontal edges for a plurality of consecutive video frames;
(f) projecting each of the dominant horizontal edges onto a ground plane;
(g) treating each pair of adjacent projected edges as a projected surface;
(h) calculating changes in the projected surface; and
(i) calculating distinct structural signatures from the changes in the projected surfaces.
10. The system of claim 9, wherein the computer processing unit further comprises a memory arrangement, a processing unit and an optional display unit for displaying data andor classification of the distinct structures in the class.
11. The system of claim 9, wherein the camera captures video images.
12. The system of claim 9, further comprising classifying the distinct structural signatures in a class based on the distinct structural signatures.
13. The system of claim 12, further comprising separating asymmetric parts of the moving objects and classifying them as non-vehicles.
14. The system of claim 13, further comprising after separating asymmetric parts of the moving objects and classifying them as non-vehicles, projecting a lower edge of the blob onto the road surface using the transformation in classification step (a).
15. A computer program product comprising a non-transitory computer usable medium having a computer readable code embodied therein for classification of passenger vehicles and measuring their properties from a rear view video frame, the computer readable program code is configured to execute a process, which includes the steps of:
(a) calibrating a transformation angle between a camera image and a road surface;
(b) detecting moving objects on the road surface in the camera image;
(c) establishing a vertical axis of symmetry for each of the moving objects;
(d) detecting dominant horizontal edges intersecting with the vertical axis of symmetry for each of the moving objects;
(e) tracking the dominant horizontal edges for a plurality of consecutive video frames;
(f) projecting each of the dominant horizontal edges onto a ground plane;
(g) treating each pair of adjacent projected edges as a projected surface;
(h) calculating changes in the projected surface; and
(i) calculating distinct structural signatures from the changes in the projected surfaces.
16. The product of claim 15, further comprising classifying the distinct structural signatures in a class based on the distinct structural signatures.
17. The product of claim 16, wherein the moving object is a motor vehicle and the class includes one of the following sedan, pickup, minivan and sport utility vehicle (SUV).
18. The product of claim 17, further comprising separating asymmetric parts of the moving objects and classifying them as non-vehicles.
19. The product of claim 18, further comprising after separating asymmetric parts of the moving objects and classifying them as non-vehicles, projecting a lower edge of the blob onto the road surface using the transformation in classification step (a).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. A circuit configuration for active control of an operating point of a bipolar transistor in a power amplifier circuit, comprising:
a balanced circuit having a first bipolar transistor and a second bipolar transistor, said first bipolar transistor having a control input, a collector and an emitter, said second bipolar transistor having a control input, a collector and an emitter;
a third transistor connected as a common emitter amplifier circuit and having a control input, a collector and an emitter, said control input of said third transistor connected to said collector of said second bipolar transistor;
a fourth transistor connected as a common emitter amplifier circuit and having a control input, a collector and an emitter, said control input of said fourth transistor connected to said collector of said third transistor;
a fifth transistor connected as a common collector circuit and having a control input, a collector and an emitter, said control input of said fifth transistor connected to said collector of said fourth transistor and said emitter of said fifth transistor connected to said control input of said second bipolar transistor;
a resistor connected to said collector of said second bipolar transistor; and
a voltage source connected to said resistor and through said resistor to said collector of said second bipolar transistor.
2. The circuit configuration according to claim 1, including a further resistor connected between said control input of said first bipolar transistor and said control input of said second bipolar transistor.
3. The circuit configuration according to claim 1,
wherein said collector of said fifth transistor is connected to said voltage source;
including a second resistor connected between said collector of said fourth transistor and said voltage source; and
including a third resistor connected between said collector of said third transistor and said voltage source.
4. The circuit configuration according to claim 1, wherein said first bipolar transistor, said second bipolar transistor, said third transistor, said fourth transistor and said fifth transistor are selected from the group consisting of npn bipolar transistors and heterobipolar transistors.
5. The circuit configuration according to claim 3, including:
a reference ground potential plane;
a fourth resistor connected between said control input of said third transistor and said reference ground potential plane;
a fifth transistor connected between said collector of said second bipolar transistor and said control input of said third transistor; and
a sixth resistor connected between said collector of said third transistor and said control input of said third transistor.
6. The circuit configuration according to claim 1, wherein said first bipolar transistor and said second bipolar transistor are constructed and disposed with respect to one another in such a manner that they have equivalent thermal characteristics.
7. The circuit configuration according to claim 1, including and integrated circuit, and said first bipolar transistor and said second bipolar transistor are disposed in an immediate vicinity of one another in said integrated circuit.
8. The circuit configuration according to claim 1, wherein said second bipolar transistor is part of said first bipolar transistor.
9. The circuit configuration according to claim 1, wherein said first bipolar transistor and said second bipolar transistor are heterobipolar transistors formed from one of a GaAs, an InGaP and a SiGe heterobipolar transistor manufacturing process.
10. The circuit configuration according to claim 3, including
a reference ground potential plane; and
a plurality of capacitors, one of said capacitors is in each case connected between said reference ground potential plane and said control input of one of said second bipolar transistor, said third transistor, said fourth transistor and said fifth transistor.
11. The circuit configuration according to claim 3, including:
a reference ground potential plane;
a fourth resistor connected between said reference-ground potential and said emitter of said third transistor; and
a fifth resistor connected between said reference-ground potential and said emitter of said fourth transistor.
12. A circuit configuration for controlling at least two operating points of a bipolar transistor in a power amplifier circuit, the circuit configuration comprising:
a first balanced circuit having a first bipolar transistor and a second bipolar transistor each with a control input, a collector and an emitter, said first balanced circuit being active in a first circuit state so that a first current through said collector of said second bipolar transistor produces a first balanced current through said collector of said first bipolar transistor;
a first active feedback circuit connected between said collector and said control input of said second bipolar transistor, a voltage at said collector of said second bipolar transistor being fed back through said first active feedback circuit to said control input of said second bipolar transistor;
a second balanced circuit formed of said first bipolar transistor and a third bipolar transistor having a control input, a collector and an emitter, said second balanced circuit being active in a second circuit state so that a second current through said collector of said third bipolar transistor produces a second balanced current through said collector of said first bipolar transistor;
a second feedback circuit connected between said collector and said control input of said third bipolar transistor, a voltage at said collector of said sixth transistor being fed back through said second feedback circuit to said control input of said third bipolar transistor; and
a switch circuit for switching between the first circuit state and the second circuit state.
13. The circuit configuration according to claim 12, including:
a resistor connected to said collector of said second bipolar transistor; and
a voltage source connected to said resistor, said collector of said second bipolar transistor is electrically connected to said voltage source through said resistor.
14. The circuit configuration according to claim 12, wherein said second feedback circuit is a line with a non-reactive resistor.
15. The circuit configuration according to claim 12, including:
a voltage source; and
a resistor connected to said voltage source, said collector of said third bipolar transistor is electrically connected to said voltage source through said resistor.
16. The circuit configuration according to claim 12, wherein said first active feedback circuit has voltage amplifiers.
17. The circuit configuration according to claim 12, wherein said first active feedback circuit has a low-impedance output stage.
18. The circuit configuration according to claim 17, wherein said low-impedance output stage of said first active feedback circuit has a high impedance below a minimum threshold voltage difference between a collector voltage and a control input voltage of said second bipolar transistor.
19. The circuit configuration according to claim 12, wherein said first active feedback circuit has a transistor with an output stage connected as a common collector circuit.
20. The circuit configuration according to claim 12,
wherein said first active feedback circuit includes a fourth transistor connected as a common emitter amplifier circuit and having a control input, a collector and an emitter, said control input of said fourth transistor connected to said collector of said second bipolar transistor; wherein said first active feedback circuit includes a fifth transistor connected as a common emitter amplifier circuit and having a control input, a collector and an emitter, said control input of said fifth transistor connected to said collector of said fourth transistor;
wherein said first active feedback circuit includes a sixth transistor connected as a common collector circuit and having a control input, a collector and an emitter, said control input of said sixth transistor connected to said collector of said fifth transistor and said emitter of said sixth transistor connected to said control input of said second bipolar transistor;
including a resistor connected to said collector of said second bipolar transistor; and
including a voltage source connected to said resistor and through said resistor to said collector of said second bipolar transistor.
21. The circuit configuration according to claim 12, including a resistor connected between said control input of said third bipolar transistor and both of said first bipolar transistor and said second bipolar transistor, said resistor having a considerably greater resistance than an output impedance of said first active feedback circuit when in a non-high-impedance state.
22. The circuit configuration according to claim 12, wherein in the second circuit state, said switch circuit sets a collector voltage of said second bipolar transistor to a threshold voltage level which is less than the collector voltage of the second bipolar transistor in the first circuit state.
23. The circuit configuration according to claim 22, wherein said switch circuit has a resistor and a transistor disposed in series with each other and in parallel with said second bipolar transistor, said transistor of said switch circuit has a control input and a collector, said collector of said transistor of said switch circuit connected through said resistor of said switch circuit to said collector of said second bipolar transistor, and said transistor of said switch circuit is switched off in the first circuit state and switched on in the second circuit state by applying a control voltage to said control input of said transistor of said switch circuit.
24. The circuit configuration according to claim 12, including a resistor connected between said control input of said second bipolar transistor and both of said control input of said first bipolar transistor and said control input of said third bipolar transistor.
25. The circuit configuration according to claim 12, including a resistor connected between said control input of said first bipolar transistor and both of said control input of said second bipolar transistor and said control input of said third bipolar transistor.
26. The circuit configuration according to claim 12, wherein said first bipolar transistor is part of a power amplifier stage having an amplifier input and a coupling capacitance connected between said amplifier input and said control input of said first bipolar transistor.
27. The circuit configuration according to claim 26, wherein said power amplifier stage is a common emitter amplifier.
28. The circuit configuration according to claim 12, wherein said first bipolar transistor, said second bipolar transistor and said third bipolar transistor are constructed and disposed with respect to one another in such a manner that they have equivalent thermal characteristics.
29. The circuit configuration according to claim 12, including an integrated circuit, and said first bipolar transistor, said second bipolar transistor and said third bipolar transistor are disposed in an immediate vicinity of one another in said integrated circuit.
30. The circuit configuration according to claim 12, wherein said first bipolar transistor, said second bipolar transistor and said third bipolar transistor are heterobipolar transistors.
31. The circuit configuration according to claim 12, wherein the circuit configuration is used in a mobile telephone.
32. The circuit configuration according to claim 12, wherein said second feedback circuit is a line without a non-reactive resistor.
33. The circuit configuration according to claim 12, wherein said first active feedback circuit has two series-connected common emitter amplifiers.
34. The circuit configuration according to claim 30, wherein said heterobipolar transistors are formed from one of a GaAs, InGaP and SiGe heterobipolar transistor manufacturing process.