1. A tool for sharpening a cutting edge and cleaning between adjacent cutting edges, the tool comprising:
an elongate gripping section having a first end and a second end;
means for sharpening extending from the first end; and
means for cleaning extending from the second end.
2. The tool of claim 1 wherein the means for sharpening comprises:
a V-shaped abrasive surface that receives the edge to be sharpened.
3. The tool of claim 1, wherein the means for cleaning comprises:
a strip of resilient material having a periphery that can be moved adjacent to an area to be cleaned from which debris can be removed by inserting the strip and moving it laterally and inwardly and outwardly.
4. The tool of claim 2, wherein the V-shaped abrasive surface includes jaws that have edges that are rounded to avoid injury.
5. The tool of claim 1, wherein the means for cleaning and the second end of the elongate gripping section 18 are connected by a neck portion.
6. The tool of claim 1, further includes a gripping surface that is disposed at least partially on the elongate gripping section.
7. The tool of claim 1, wherein the means for cleaning and the second end of the elongate gripping section are connected by a tapered section of the second end of the elongate gripping section.
8. The tool of claim 3, wherein the strip of resilient material has a periphery with square edges.
9. A method for using a tool for sharpening a razorblade, the tool having an elongate gripping section, a sharpening means, and a cleaning means, the method comprising the steps of:
moving an edge to be rejuvenated in relation to the sharpening means;
sliding the sharpening means laterally in relation to the edge to be rejuvenated, thus forming a rejuvenated edge; and
removing the rejuvenated edge from the sharpening means.
10. A method for cleaning between adjacent cutting edges, the method comprising the steps of inserting a cleaning means that extends from an end of a tool between blades to be sharpened;
moving the cleaning means laterally in relation to the space that contains debris to be dislodged; and
removing the cleaning means.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processor comprising:
instruction hardware to receive a plurality of instructions, each having one of a plurality of instruction types, including an accelerator job request instruction type; and
execution hardware to execute the accelerator job request instruction type to cause the processor to submit a job request to an accelerator and return a transaction identification value.
2. The processor of claim 1, wherein the processor is connected to the accelerator on a system on a chip.
3. The processor of claim 1, wherein the accelerator job request instruction type includes an accelerator identifier field.
4. The processor of claim 3, wherein the plurality of instruction types also includes an accelerator identification instruction type, and the execution hardware is to execute the accelerator identification instruction type to cause the processor to provide a value for the accelerator identifier field identification.
5. The processor of claim 1, wherein the plurality of instruction types also includes a virtual machine enter instruction type, and the execution hardware is to execute the virtual machine entry instruction type to cause the processor to transfer from a root mode to a non-root mode for executing guest software in at least one virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events, and wherein the processor is to execute the accelerator job request instruction type without causing a virtual machine exit.
6. The processor of claim 1, further comprising storage to store an accelerator job queue, the accelerator job queue having a plurality of entry locations, each entry location to store a transaction identifier, an accelerator identifier, a context identifier, and a status.
7. A method comprising:
receiving, by a processor, a first instruction, the first instruction having an accelerator job request instruction type; and
executing, by the processor, the first instruction to subunit a job request to an accelerator.
8. The method of claim wherein the processor is connected to the accelerator on a system on a chip.
9. The method of claim 7, further comprising identifying the accelerator from a value in a field of the first instruction.
10. The method of claim 7, further comprising:
receiving, by the processor, a second instruction, the second instruction having accelerator identification instruction type; and
executing, by the processor, the second instruction to cause the processor to provide identification information for an accelerator to accept a job request.
11. The method of claim 7, further comprising:
receiving, by the processor, a third instruction, the third instruction having a virtual machine enter instruction type; and
executing, by the processor, the third instruction to cause the processor to transfer from a root mode to a non-root mode for executing guest software in at least one virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events, and wherein the processor is to execute the accelerator job request instruction type without causing a virtual machine exit.
12. The method of claim 7, further comprising returning, by the processor, a transaction identifier in response to receiving the first instruction.
13. The method of claim 7, further comprising submitting, by the processor, the job request to an accelerator job queue.
14. The method of claim 13, further comprising submitting, by the processor, a context identifier to the accelerator job queue.
15. The method of claim 14, further comprising translating, by an inputoutput memory management unit, an address for the job request.
16. The method of claim 15, further comprising using the context identifier to enforce address domain isolation without causing a virtual machine exit.
17. A system comprising:
a hardware accelerator; and
a processor including
instruction hardware to receive a plurality of instructions, each having one of a plurality of instruction types, including an accelerator job request instruction type, and
execution hardware to execute the accelerator job request instruction type to cause the processor submit a job request to the hardware accelerator and return a transaction identification value.
18. The system of claim 17, wherein the plurality of instruction types also includes an accelerator identification instruction type, and the execution hardware is to execute the accelerator identification instruction type to cause the processor to provide an identification information associated with the accelerator.
19. The system of claim 17, wherein the plurality of instruction types also includes a virtual machine enter instruction type, and the execution hardware is to execute the virtual machine entry instruction type to cause the processor to transfer from a root mode to a non-root mode for executing guest software in at least one virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events.
20. The system of claim 19, further comprising an inputoutput memory management unit to translate an address for the job request using a context identifier to enforce address domain isolation without causing a virtual machine exit, the context identifier provided by the processor to the accelerator in connection with the job request.