1. A system for simultaneously routing and grounding coaxial cable on a printed circuit board, the system comprising:
a metal sheath external to a coaxial cable, the sheath coupled electrically and mechanically to the coaxial cable with a protrusion configured to pierce or break an outer insulation of the coaxial cable and form an electrical pathway between the sheath and a shield of the coaxial cable;
a clip coupled electrically and mechanically to the printed circuit board, the clip comprising:
a resilient metal;
a rectangular bottom surface having two sides and two ends;
a pair of side walls extending upward from the sides of the bottom surface;
an inward bend feature on each side wall defining a gap between a distal portion of the side walls that is less than a diameter of the sheath, thereby retaining the sheath within the side walls and engaging the sheath mechanically and electrically; and
a pair of top flanges, each flange being substantially parallel to the bottom surface and extending away from an upper edge of the inward bend and wherein a total surface area of the top flanges is greater than a total surface area of the bottom surface.
2. The system of claim 1, wherein the resilient metal is a nickel silver alloy.
3. The system of claim 1, the conductive clip further comprising a mounting tab extending from each of the ends of the conductive clip.
4. A system comprising:
an insulated cable;
a sheath external to the cable and electrically and mechanically coupled to the insulated cable, wherein the sheath is conductive and is configured to pierce or break an outer insulation of the insulated cable and form an electrical pathway between the sheath and a shielding of the insulated cable;
a backplane; and
a clip mechanically and electrically coupled to the backplane and configured to electrically and mechanically engage the sheath, the clip comprising:
a resilient and conductive material;
a substantially rectangular bottom surface coupled to the backplane;
a first side wall extending upward from an edge of the bottom surface and configured to retain the insulated cable and the sheath and establish an electrical connection with the sheath, and
a top flange extending from the first side wall substantially parallel to the bottom surface and having a total surface area at least equal to a total surface area of the bottom surface.
5. The system of claim 4, wherein the resilient material comprises a metal or a polymer.
6. The system of claim 4, wherein the backplane comprises a printed circuit board.
7. The system of claim 4, further comprising a second side wall extending upward from an edge of the bottom surface opposite the first side wall and configured to retain the cable.
8. The system of claim 4, wherein the cable comprises coaxial cable.
9. The system of claim 4, wherein the sheath is substantially circular in cross section.
10. The system of claim 4, wherein the sheath has a substantially square or substantially rectangular cross section.
11. A clip for routing and grounding a cable on a backplane, the clip comprising:
a conductive body configured to accept a conductive sheath, the conductive sheath configured to electrically engage a portion of the cable, wherein the conductive sheath is external to the cable and configured to pierce or break an outer insulation of the cable and form an electrical pathway between the conductive sheath and a shield of the cable; and
one or more top flanges coupled to the conductive body, the one or more top flanges combined having a total surface area at least equal to a total surface area of a bottom surface of the conductive body.
12. The clip of claim 11, wherein the conductive body further comprises:
a substantially rectangular bottom surface having two sides and two ends;
a pair of side walls extending upward substantially vertically from the sides of the bottom surface;
an inward bend on each side wall defining a gap between the distal portion of the side walls of less than a diameter of the cable thereby configured to retain the conductive sheath within the side walls and engage the conductive sheath mechanically and electrically; and
the one or more top flanges, each flange being substantially parallel to the bottom surface and extending away from an upper edge of the inward bend.
13. The clip of claim 11, wherein the conductive body further comprises:
a substantially rectangular bottom surface having two sides and two ends;
a pair of side walls extending upward substantially vertically from the sides of the bottom surface, the walls being curved to match a profile of the conductive sheath and coupled to the one or more top flanges;
an inward bend on each side wall defining a gap between the distal portion of the side walls of less than a diameter of the cable, thereby configured to retain the conductive sheath within the side walls and engage the conductive sheath mechanically and electrically.
14. The clip of claim 11, wherein the conductive body comprises a polymer.
15. The clip of claim 11, wherein the conductive sheath has a substantially square or substantially rectangular cross section.
16. The clip of claim 11, further comprising tabs protruding from the conductive body for attachment to the backplane.
17. A method of routing and grounding a coaxial cable on a printed circuit board, the method comprising:
mechanically coupling a conductive sheath externally to a coaxial cable;
electrically coupling the conductive sheath to a shield of the coaxial cable via a protrusion configured to pierce or break an outer insulation of the coaxial cable and form an electrical pathway between the conductive sheath and the shield;
mechanically and electrically coupling a conductive clip to a backplane ground connection, wherein the conductive clip comprises one or more top flanges coupled to a conductive body, the one or more top flanges combined having a total surface area at least equal to a total surface area of a bottom surface of the conductive body; and
inserting the conductive sheath within the conductive clip.
18. The method of claim 17, wherein mechanically and electrically coupling the conductive clip to the backplane comprises soldering the clip to the backplane.
19. The method of claim 17, wherein the electrically coupling the conductive sheath to the shield of the coaxial cable comprises crimping such that at least a portion of the conductive sheath pierces an outer insulation layer of the coaxial cable and contacts at least a portion of the shield.
20. The method of claim 17, further comprising coupling a plurality of conductive clips to a backplane to define a cable routing path.
21. The method of claim 17, wherein the coaxial cable couples a radio frequency module to an antenna.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A cell string comprising:
an insulating layer;
a semiconductor body which is formed on a surface of the insulating layer;
first and second semiconductor regions which are formed at respective ends of the semiconductor body and are formed by being doped with different types of impurities;
two or more control electrodes which are separated from each other to be electrically isolated; and
a gate insulating film stack which is formed between the semiconductor body and the control electrodes,
wherein the semiconductor body is configured to include at least two layers, and adjacent layers of the semiconductor body have different energy band gaps.
2. The cell string according to claim 1,
wherein the semiconductor body is formed by an intrinsic semiconductor or by a semiconductor being doped with impurities, and
wherein the first and second semiconductor regions are doped with impurities of which concentration is higher than that of the semiconductor body.
3. The cell string according to claim 1, wherein the gate insulating film stack is configured to include a tunneling insulating film, a charge storage node, and a blocking insulating film which are stacked in this order from the surface of the semiconductor body.
4. The cell string according to claim 1,
wherein the semiconductor body is configured to include a first layer adjacent to the gate insulating film stack and a second layer adjacent to the insulating layer,
wherein the first layer is made of a material of which band gap is larger than that of the second layer, and
wherein the second layer is made of a material of which band gap is smaller than that of the first layer.
5. The cell string according to claim 1,
wherein the semiconductor body is configured to include a first layer adjacent to the gate insulating film stack, a third layer adjacent to the insulating layer, and a second layer formed between the first layer and the third layer,
wherein the first layer and the third layer are made of a material of which band gap is larger than that of the second layer, and
wherein the second layer is made of a material of which band gap is smaller than those of the first layer and the third layer.
6. The cell string according to claim 1, where the control electrodes located at the respective ends among the two or more control electrodes are connected to a first selection line SL1 and a second selection line SL2 for selecting the cell string, respectively.
7. The cell string according to claim 1,
wherein the semiconductor body, the insulating layer, and the gate insulating film stack are arranged in a direction horizontal to the surface of the semiconductor substrate,
wherein the control electrodes are formed to be arranged in a direction vertical to the surface of the semiconductor substrate and to be electrically isolated from each other, and
where each of the control electrodes is formed to have a single-gate structure, a dual-gate or triple-gate structure, or a GAA (Gate All Around) structure.
8. The cell string according to claim 1,
wherein the semiconductor body, the insulating layer, and the gate insulating film stack are arranged in a direction vertical to the surface of the semiconductor substrate, and one end of the semiconductor body is arranged on the semiconductor substrate,
where the control electrodes are formed to be arranged in a direction horizontal to the surface of the semiconductor substrate and to be electrically isolated from each other, and
where one of the first and second semiconductor regions is formed on the surface of the semiconductor substrate.
9. The cell string according to claim 8,
wherein the insulating layer is configured to be in a cylindrical shape on the semiconductor substrate,
where the semiconductor body is configured to have a shape surrounding an outer circumferential surface of the insulating layer, and
where the gate insulating film stack and the control electrodes are sequentially formed on an outer circumferential surface of the semiconductor body.
10. A reading method for the cell string having the structure according to claim 1,
in a state where n control electrodes in the cell string are connected to respective n word lines WL0 to WLn\u22121, the first semiconductor region is connected to bit lines, and the second semiconductor region is connected to a common source line CSL,
the reading method comprising at least a step (r1) of, when a selected word line is the word line WLk (0<k<n\u22121), applying a voltage to the word lines of from the word line WLn\u22121 to at least the WLk\u22121 and applying a voltage having an opposite polarity to the remaining word lines, thereby reading information stored in the selected word line WLk.
11. The reading method according to claim 10, wherein in the step (r1), the selection line SL1 connected to the is applied with a voltage having a polarity same to that of the voltage applied to the word lines WLn\u22121 to WLk\u22121, the selection line SL2 connected to the common source line CSL is applied with a voltage having a polarity opposite to that of the voltage applied to the word lines WLn\u22121 to WLk\u22121, and a selected bit line, unselected bit lines, and the common source line CSL are applied with a same voltage.
12. The reading method according to claim 10, after the step (r1), further comprising a step (r2) of turning off the selection line SL1 and applying a voltage which is lower than a read voltage (Vverify) to the selected word line WLk.
13. The reading method according to claim 12, after the step (r2), further comprising a step (r3) of applying a voltage to the common source line CSL so that a current can flow in the cell string selected in a subsequent step and applying the voltage applied to the common source line CSL to unselected bit lines so that no current flows in a subsequent read operation.
14. The reading method according to claim 13, after the step (r3), further comprising a step (r4) of applying a voltage to the selection line SL1 so that a selection device connected to the selection line SL1 is turned on and applying the read voltage (Vverify) to the selected word line WLk,
wherein the voltage applied to the selection line SL1 and the voltage applied to the selected word line WLk are applied simultaneously or applied in a reverse order.
15. The reading method according to 13, further comprising a step of, in case of performing sensing all the bit lines, applying the voltage to the common source line CSL in the step (r3), applying a voltage which is lower than the voltage applied to the common source line CSL to all the bit lines of a selected page, and after that, applying the read voltage, so that current can flow in all the cell strings of the selected page.
16. A reading method for the cell string having the structure according to claim 1,
in a state where n control electrode in the cell string are connected to respective n word lines WL0 to WLn\u22121, the first semiconductor region is connected to bit lines, and the second semiconductor region is connected to a common source line CSL,
the reading method comprising at least steps of:
(m1) applying a voltage having the same polarity to all the word lines except for the selected word line (WLk) in the cell string, turning on any one of the selection line SL1 and the selection line SL2, applying a voltage which is lower than the read voltage (Vverify) to the selected word line WLk, and applying the same voltage to all the bit lines and the common source line CSL; and
(m2) applying a voltage to the common source line CSL and the unselected bit lines, applying the read voltage (Vverify) to the selected word line WLk, and turning on both of the selection line SL1 and the selection line SL2 to perform a read operation, thereby reading information stored in the selected word line WLk.