1. A nonvolatile semiconductor memory device comprising:
a memory cell array having a first sub-bank in which a plurality of nonvolatile memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line and a second sub-bank having the same configuration as that of the first sub-bank;
a writeread control unit that performs write or read control for a target memory cell corresponding to a designated address;
a decoder unit that applies a voltage to the bit line and the word line based on an instruction from the writeread control unit to apply a write voltage or a read voltage to the target memory cell;
a read circuit that reads written data from the target memory cell to which the read voltage is applied; and
a comparing unit that compares a plurality of data to be input, wherein,
when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank, the decoder unit executes, in the same time zone,
a first operation in which a read voltage is applied to a first target memory cell in the first sub-bank, and
a second operation in which a write voltage is applied to a second target memory cell only when a comparison result between the written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell by the comparing unit represents mismatching.
2. The nonvolatile semiconductor memory device according to claim 1, wherein,
when the respectively designated write target data are written in the plurality of target memory cells located in the first sub-bank and the second sub-bank,
the decoder unit is configured to execute an operation step including the first operation and the second operation two or more times while changing the first target memory cell and the second target memory cell, and
the second target memory cell in each of the operation steps is the first target memory cell in the previously executed operation step.
3. The nonvolatile semiconductor memory device according to claim 1, wherein
the decoder unit includes
a row decoder that is arranged in common in the first sub-bank and the second sub-bank and simultaneously applies a voltage to the corresponding word lines in the first sub-bank and the second sub-bank,
a first column decoder that applies a voltage to the bit line of the first sub-bank,
a second column decoder that applies a voltage to the bit line of the second sub-bank,
the first operation is an operation in which the first column decoder applies the read voltage to the bit line connected to the first target memory cell in a state in which the row decoder applies a voltage to the word line connected to the first target memory cell, and
the second operation is an operation in which the second column decoder applies the write voltage to the bit line connected to the second target memory cell located at the same row as the first target memory cell only when a comparison result between the written data in the second target memory cell and the write target data to the second target memory cell represents mismatching.
4. The nonvolatile semiconductor memory device according to claim 1, wherein
the memory cell array includes a plurality of memory units each configured by the first sub-bank and the second sub-bank, and
the decoder unit is provided for each of the memory units,
when the respectively designated write target data are written in the plurality of target memory cells arranged across the plurality of memory units,
the decoder units provided in the memory units in which the target memory cells are present execute the first operation and the second operation in the same time zone.
5. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell comprises a variable resistive element a resistance of which is reversibly changed depending on an applied voltage and is configured to store information depending on the resistance of the variable resistive element.
6. A method of driving a nonvolatile semiconductor memory device including a memory cell array having a first sub-bank in which a plurality of nonvolatile memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line, and a second sub-bank having the same configuration as that of the first sub-bank, wherein
when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank,
a first operation in which a read voltage is applied to a first target memory cell in the first sub-bank, and a second operation in which a write voltage is applied to a second target memory cell only when a comparison result between written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell represents mismatching are executed in the same time zone.
7. The method of driving a nonvolatile semiconductor memory device according to claim 6, wherein
an operation step including the first operation and the second operation is executed two or more times while changing the first target memory cell and the second target memory cell, and
the second target memory cell in each of the operation steps is the first target memory cell in the previously executed operation step.
8. The method of driving a nonvolatile semiconductor memory device according to claim 6, wherein
the memory cell array includes a plurality of memory units each configured by the first sub-bank and the second sub-bank, and,
when the respectively designated write target data are written in the plurality of target memory cells arranged across the plurality of memory units,
in each of the memory units in which the target memory cells are present, the first operation and the second operation are executed in the same time zone.
9. A nonvolatile semiconductor memory device comprising:
a memory cell array having a first sub-bank in which a plurality of memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line and a second sub-bank having the same configuration as that of the first sub-bank;
a writeread control unit that performs write or read control for a target memory cell corresponding to a designated address;
a decoder unit that performs a write process or a read process in the target memory cell based on an instruction from the writeread control unit;
a read circuit that reads written data from the target memory cell; and
a comparing unit that compares a plurality of data to be input, wherein,
when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank,
the decoder unit executes, in the same time zone
a first operation in which a read process is performed in a first target memory cell in the first sub-bank and
a second operation in which a write process is performed in a second target memory cell only when a comparison result between the written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell by the comparing unit represents mismatching.
10. The nonvolatile semiconductor memory device according to claim 2, wherein
the decoder unit includes
a row decoder that is arranged in common in the first sub-bank and the second sub-bank and simultaneously applies a voltage to the corresponding word lines in the first sub-bank and the second sub-bank,
a first column decoder that applies a voltage to the bit line of the first sub-bank,
a second column decoder that applies a voltage to the bit line of the second sub-bank,
the first operation is an operation in which the first column decoder applies the read voltage to the bit line connected to the first target memory cell in a state in which the row decoder applies a voltage to the word line connected to the first target memory cell, and
the second operation is an operation in which the second column decoder applies the write voltage to the bit line connected to the second target memory cell located at the same row as the first target memory cell only when a comparison result between the written data in the second target memory cell and the write target data to the second target memory cell represents mismatching.
11. The nonvolatile semiconductor memory device according to claim 2, wherein
the memory cell array includes a plurality of memory units each configured by the first sub-bank and the second sub-bank, and
the decoder unit is provided for each of the memory units,
when the respectively designated write target data are written in the plurality of target memory cells arranged across the plurality of memory units,
the decoder units provided in the memory units in which the target memory cells are present execute the first operation and the second operation in the same time zone.
12. The nonvolatile semiconductor memory device according to claim 2, wherein the memory cell comprises a variable resistive element a resistance of which is reversibly changed depending on an applied voltage and is configured to store information depending on the resistance of the variable resistive element.
13. The method of driving a nonvolatile semiconductor memory device according to claim 7, wherein
the memory cell array includes a plurality of memory units each configured by the first sub-bank and the second sub-bank, and,
when the respectively designated write target data are written in the plurality of target memory cells arranged across the plurality of memory units,
in each of the memory units in which the target memory cells are present, the first operation and the second operation are executed in the same time zone.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An ice making machine comprising:
a heat exchange system comprising an evaporator and a condenser configured to make ice pieces with water applied to said evaporator during a freeze cycle; and
a controller that controls a start time and an end time of the freeze cycle, wherein the start time begins only if a temperature of said water is 32 degrees F. or lower and the end time is based on a temperature of refrigerant exiting said condenser when the start time begins.
2. The ice making machine of claim 1, wherein the end time is determined from a table of time versus condenser refrigerant exit temperatures at a time when the water is approximately 32 degrees F.
3. The ice making machine of claim 1, wherein said heat exchanger system further comprises one or more sprayers that spray the water on the evaporator.
4. The ice making machine of claim 1, further comprising a first temperature sensor located in the water and a second temperature sensor located to sense the temperature of the refrigerant exiting the condenser, and wherein the start and end times are determined based on temperatures sensed by the first and second temperature sensors.
5. The ice making machine of claim 1, further comprising a processor and program module associated with the controller, wherein the processor executes instructions of the program module to determine the start time and the end time of the freeze cycle.
6. A method of controlling ice making of an ice making machine comprising:
configuring an evaporator and a condenser to make ice pieces with water applied to said evaporator during a freeze cycle;
controlling a start time of the freeze cycle to begin only if a temperature of said water is 32 degrees F. or lower; and
controlling an end time of the freeze cycle based on a temperature of refrigerant exiting said condenser when the start time begins.
7. The method of claim 6, further comprising:
determining the end time from a table of time versus condenser refrigerant exit temperatures at a time when the water is approximately 32 degrees F.
8. The method of claim 6, further comprising:
locating a first temperature sensor to sense a temperature of the water;
locating a second temperature sensor to sense a temperature of refrigerant exiting the condenser, and wherein the start and end times are determined based on the temperatures sensed by the first and second temperature sensors.
9. The method of claim 6, further comprising:
executing instructions of a program module to determine the start time and end time of the freeze cycle.
10. The method of claim 6, further comprising:
spraying the water on the evaporator.