1. A device for the controlled generation of an electric arc, comprising:
a system for striking an electric arc on the terminals of two electrodes through inductive switching, producing at its output an overvoltage on the terminals of these electrodes; and
an electrical power source connected in series to the output of the striking system, said source supplying the electric arc with current.
2. The device as claimed in claim 1, wherein the electrical power source is a voltage generator, an electric load defining the value of the current.
3. The device as claimed in claim 1, wherein the electrical power source is a current generator, an electric load defining the value of the current.
4. The device as claimed in claim 1, wherein the striking system comprises at least a transformer, a primary voltage generator and a switch connected in series with the primary coil of said transformer, the overvoltage on the terminals of the electrodes being generated on the terminals of the secondary coil of the transformer when the switch is in the closed position.
5. The device as claimed in claim 4, wherein the duration of closure of the switch is controllable.
6. The device as claimed in claim 1, wherein the electric load is connected in series with the electrical power source.
7. The device as claimed in claim 1, wherein the electric load is connected in parallel with the electrical power source.
8. The device as claimed in claim 6, wherein the value of the electric load is controllable.
9. The device as claimed in claim 2, wherein the voltage at the output of the voltage generator is direct.
10. The device as claimed in claim 2, wherein the voltage at the output of the voltage generator is alternating.
11. The device as claimed in claim 1, wherein the electrodes are placed in a container in which environmental conditions are simulated.
12. The device as claimed in claim 11, wherein the container comprises a controllable heating and cooling system.
13. The device as claimed in claim 11, further comprising a controllable vacuum pump connected to the container to control the pressure inside said container.
14. The device as claimed in claim 1, further comprising a system to move the electrodes away from or towards one another, said system being controllable.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory control device for controlling either write-in or read-out operation for a memory, the memory control device comprising:
an interface unit connected to the memory for performing either write-in or read-out operation for the memory;
a power-on reset signal generation unit for generating a power-on reset signal in response to power on;
an internal reset signal generation unit for generating a an internal reset signal in response to a reset request;
an initializing signal supply unit for delivering the power-on reset signal or the internal reset signal as an initializing signal that initializes write-in status or read-out status information data held by the interface unit to the interface unit; and
a control unit for determining whether or not the initializing signal is based on the power-on reset signal after the write-in status or read-out status information data in the interface unit is initialized in response to the initializing signal, and for performing a check process on the memory if the initializing signal is determined to be based on the power-on reset signal.
2. The memory control device according to claim 1, further comprising a storage unit for storing a power-on reset code representative of completion of delivery of a first initializing signal which is the initializing signal delivered at first time after power on, and wherein
the control unit determines whether or not the power-on reset code is stored in the storage unit in response to the initializing signal, and if the control unit determines that the power-on reset code is not stored, the control unit writes the power-on reset code to the storage unit and determines that the initializing signal is based on the power-on reset signal.
3. The memory control device according to claim 1, wherein
the memory is divided into a plurality of blocks, and
the control unit performs the check process on some region of each of the blocks.
4. The memory control device according to claim 3, wherein
the plurality of blocks are each divided into a plurality of pages, and
whenever the power on is performed, the control unit changes a target page for the check process among the plurality of pages and performs the check process on the target page in each of the blocks.
5. The memory control device according to claim 3, wherein
the check process includes an error detection process that performs error detection on data read from the memory and generates information indicative of number of error bits, and
the control unit executes an error correction process on a block, among the plurality of blocks, which includes data in which the number of error bits exceeds a specified threshold value.
6. The memory control device according to claim 5, wherein
the control unit executes the error correction process, if the reset signal is determined to be based on the power-on reset signal.
7. The memory control device according to claim 5, wherein
the control unit stores information indicative of number of the target pages for the check process and information indicative of maximum number of blocks, on which the error correction process is performed, as management information in the memory, and executes the check process and the error correction process on the basis of the management information.
8. A memory control method for controlling either write-in or read-out operation for a memory, the memory control method comprising the steps of:
generating a power-on reset signal in response to power on;
generating an internal reset signal in response to a reset request;
delivering the power-on reset signal or the internal reset signal as an initializing signal; and
determining whether or not the initializing signal is based on the power-on reset signal and performing a check process on the memory only when the initializing signal is determined to be based on the power-on reset signal.
9. The memory control method according to claim 8, further comprising the step of storing a power-on reset code representative of completion of delivery of a first initializing signal which is the initializing signal delivered at first time after the power on, and wherein
in the step of performing the check process, it is determined whether or not the power-on reset code is stored in response to the initializing signal, and if it is determined that the power-on reset code is not stored, the power-on reset code is written and the initializing signal is determined to be based on the power-on reset signal.
10. The memory control method according to claim 8, wherein
the memory is divided into a plurality of blocks, and
in the step of performing the check process, the check process is performed on some region of each of the blocks.
11. The memory control method according to claim 10, wherein
the plurality of blocks are each divided into a plurality of pages, and
in the step of performing the check process, whenever the power on is performed, a target page for the check process is changed among the plurality of pages and the check process is performed on the target page in each of the blocks.
12. The memory control method according to claim 10, wherein
the check process includes an error detection process that performs error detection on data read from the memory and generates information indicative of number of error bits, and
the method further includes the step of executing an error correction process on a block, among the plurality of blocks, which includes data in which the number of error bits exceeds a specified threshold value.
13. The memory control method according to claim 12, wherein the step of executing the error correction process includes the step of executing the error correction process if the reset signal is determined to be based on the power-on reset signal.
14. The memory control method according to claim 12, further comprising the step of storing information indicative of number of the target pages targeted to the check process and information indicative of maximum number of blocks, on which the error correction process is performed, as management information in the memory, and wherein
the step of executing the check process includes the step of executing the check process on the basis of the management information, and
the step of executing the error correction process includes the step of executing the error correction process on the basis of the management information.