1. A computer implemented method comprising steps of: converting lines of source code representing functions to byte-codes representing functions;
selecting a subsequence of byte-codes based on the byte-codes and dynamic run-time properties of variables referenced by the byte-codes;
generating processor instructions in a compiler for the subsequence; and
generating alternate byte-codes in an accelerated interpreter for at least a portion of the byte-codes not contained in the subsequence.
2. The method of claim 1 in which the properties comprise at least one of variable type or variable shape.
3. The method of claim 2 in which selecting comprises:
analyzing the type and shape of the variables referenced by the byte-codes; and
determining whether at least one of the type or shape is modified.
4. The method of claim 3 in which selecting further comprises:
adding the byte-codes to the subsequence if the type and shape is not modified.
5. The method of claim 4 in which the subsequence represents a compilation unit.
6. The method of claim 1 further comprising executing the processor instructions in a processor.
7. The method of claim 1 further comprising:
reverting a compilation unit to interpreted byte-codes; and
removing the byte-codes in the subsequence of lines in which the type or shape of variables has changed.
8. A computer implemented method comprising steps of:
converting lines of source code representing functions to byte-codes representing functions;
selecting a subsequence of byte-codes based on the byte-codes and dynamic run-time properties of variables referenced by the byte-codes;
generating processor instructions in a compiler for the subsequence;
interpreting the byte-codes not contained in the subsequence;
reverting a compilation unit to interpreted byte-codes; and
determining whether the byte-codes that are members of the subsequence can remain in the subsequence.
9. The method of claim 8 in which determining comprises:
analyzing an original type and shape of a variable; and
determining whether a new type and a new shape of variable can be represented by the original type and original shape of variable.
10. The method of claim 8 in which determining comprises:
analyzing an original type and shape of a variable; and
determining whether the byte-codes can be compiled to processor instructions that can process both the original type and shape of the variable and the modified type and shape of the variable.
11. A computer implemented method comprising steps of:
converting lines of source code representing functions to byte-codes representing functions;
selecting a subsequence of byte-codes based on the byte-codes and dynamic run-time properties of variables referenced by the byte-codes;
generating alternate byte-codes in an accelerated interpreter for the subsequence; and
interpreting the byte-codes not contained in the subsequence by a second interpreter.
12. The method of claim 11 in which selecting comprises:
determining type and shape of variables referenced by the byte-codes; and
resolving dynamic variable and constant value references to an absolute memory address.
13. The method of claim 12 in which resolving comprises determining:
whether an expression requires one or more temporary results; and
storing the temporary results in memory locations that are determined at compile time.
14. The method of claim 12 in which resolving comprises:
using a composition of an expression to group operations of an element-wise expression into a single compound operation.
15. A computer implemented method comprising steps of:
converting source code representing functions to byte-codes representing functions;
selecting a first subsequence of byte-codes based on the byte-codes and dynamic run-time state of program variables;
selecting a second subsequence of byte-codes based on the byte-codes and the dynamic run-time state of program variables;
generating processor instructions in a compiler for the first subsequence;
generating alternate byte-codes in an accelerated interpreter for the second subsequence; and
interpreting the byte-codes not contained in the first subsequence and the second subsequence.
16. The method of claim 15 in which selecting the first subsequence comprises:
analyzing type and shape of the variables referenced by the byte-codes;
determining whether the type and shape is modified; and
adding the byte-codes to the subsequence if the type and shape is not modified.
17. The method of claim 15 in which selecting the second subsequence comprises:
determining the type and shape of variables referenced by the byte-codes; and
resolving dynamic variable and constant value references to an absolute memory address.
18. The method of claim 15 in which selecting the second subsequence comprises:
using a structure of an expression to group operations of an element-wise expression into a single compound operation.
19. A computer implemented system comprising steps of:
a first interpreter in a memory for converting source code into bytes-codes representing functions;
an analysis unit in the memory for analyzing whether the byte-codes can be stored in a subsequence of byte-codes;
a compiler for compiling byte-codes in the subsequence to processor instructions; and
a second compiler for converting byte-codes not resident in the subsequence to alternate byte-codes.
20. The system of claim 19 further comprising a second interpreter for executing the alternate byte-codes.
21. The system of claim 19 further comprising a processor for executing the processor instructions.
22. The system of claim 21 further comprising an inputoutput device for receiving the source code and displaying results after execution of the processor instructions.
23. The system of claim 19, wherein the first interpreter, the compiler, or the second compiler executes on a first processor or a second processor.
24. An article comprising:
a storage medium having stored thereon instructions that when executed by a machine results in the following:
converting lines of source code representing functions to byte-codes representing functions;
selecting a subsequence of byte-codes based on the byte-codes and dynamic run-time properties of variables referenced by the byte-codes;
generating processor instructions in a compiler for the subsequence; and
generating alternate byte-codes in an accelerated interpreter for at least a portion of the byte-codes not contained in the subsequence.
25. An article comprising a storage medium having stored thereon instructions that when executed by a machine results in the following:
converting source code representing functions to byte-codes representing functions;
selecting a first subsequence of byte-codes based on the byte-codes and the dynamic run-time state of program variables;
selecting a second subsequence of byte-codes based on the byte-codes and dynamic run-time state of program variables;
generating processor instructions in a compiler for the first subsequence;
generating alternate byte-codes in an accelerated interpreter for the second subsequence; and
interpreting the byte-codes not contained in the first subsequence and the second subsequence.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A bus, having at least an address remapper defining two sections in the bus, each section comprising at least one station having a physical address, wherein stations on each section of the bus are each assigned a dummy address for being addressed by a station on the other section, the address remapper remapping a dummy address from one section into a physical address to the other section.
2. A bus according to claim 1, wherein the format of a physical address comprises a fixed part and a setable part, and wherein the dummy address is obtained by changing at least one bit of the fixed part of the physical address.
3. A bus according to claim 1, wherein the dummy addresses for stations out of a given section are different from the physical addresses for stations in said given section.
4. An address remapper for a bus, comprising:
terminals for connecting two sections of the bus;
address detecting means for detecting an address received from one section of the bus;
address remapping means for remapping the address and transmitting the remapped address to the other section of the bus.
5. An address remapper according to claim 4, wherein the bus is a two wire serial bus, and wherein the address detecting means detect a transition of the value on one wire while the other wire is a given level.
6. An address remapper according to claim 4, wherein the bus is a two wire serial bus, and wherein the address remapping means comprise means for bringing one wire to a given level.
7. An address remapper according to claim 4, wherein the bus is a two wire serial bus having one data wire and one clock wire, the terminals for the clock wire of each section being connected.
8. An address remapper according to claim 7, wherein the address remapping means includes switching means for selectively disconnecting the bus during the remapping operation.
9. A process for connecting two sections of a bus, by transmitting data from one section of the bus to the other section of the bus, comprising the steps of
detecting an address sent from one section of the bus to the other section of the bus;
remapping the address before transmitting it to the other section of the bus.
10. A process according to claim 9, wherein the step of detecting comprises detecting a START condition preceding an address.
11. A process according to claim 10, wherein the step of remapping comprises changing at least one bit of an address, preferably one bit of a fixed part of an address.
12. A computer system including a bus, having at least an address remapper defining two sections in the bus, each section comprising at least one station having a physical address, wherein a station on one section of the bus is assigned a dummy address for being addressed by a station on the other section, the address remapper remapping a dummy address from the other section into a physical address to the one section.
13. A computer system according to claim 12, wherein the format of a physical address comprises a fixed part and a setable part, and wherein the dummy address is obtained by changing at least one bit of the fixed part of the physical address.
14. A computer system according to claim 12, wherein the dummy addresses for stations out of a given section are different from the physical addresses for stations in said given section.
15. A bus having at least an address remapper defining at least two sections of the bus, each section of the bus having at least one station having a physical address and wherein each station in each section of the bus is assigned a dummy address for use when being addressed by a station on the other bus section, the address remapper remapping dummy addresses on either section of the bus into a corresponding physical address on the other section of the bus.
16. The bus of claim 15 wherein a station on one portion of the bus and another station on the other portion of the bus share a common physical address.
17. A bus as claimed in claim 15 wherein the address remapping is performed by changing at least one bit of the address of each station.
18. A bus, having at least an address remapper defining two sections in the bus, each section including at least one station having a physical address, wherein each station on each section of the bus is assigned a dummy address by the remapper for the purpose of being addressed by a station on the other section, the address remapper transparently remapping each dummy address from one section into a physical address on the other section.