1. An automatic optical inspection tool of an apparatus for residue detection on polished wafer surface, comprising:
an illumination source disposed at an angle to said surface, and capable of instantaneous illumination of the entire wafer surface;
colour digital camera disposed at an angle to said surface opposite to the angle of said illumination source and capturing reflected light from the entire wafers surface without eclipse, in a duple of consecutive, properly delayed imaging shots and providing appropriate image resolution for tiny residue detection;
computation means, implementing image processing and manipulation algorithms to enable residue detection and characterization and providing for logic and command operations execution and camera control;
said computation means accumulating an on-line created wafer images and wafer residue defects data base, and
providing for inspection tool worthiness monitoring.
2. The apparatus as claimed in claim 1, further comprising:
a parent tool wafer-handling and transportation means contained in an output stage robot;
said inspection tool includes a support structure, mounted on a parent tool chassis;
said computation means including an information exchange interface with a parent tool operator via computer screen, with process floor host, and with the parent tool electrical trigger module, and
said parent tool operator executing the man-in-the-loop control functions.
3. The apparatus as claimed in claim 2, wherein said inspection tool is an on-process integrated added-on washer-scrubber tool or an integrated polishing machine.
4. The apparatus as claimed in claim 1, wherein said inspection process of said inspection tool and results analysis and action taken, is controlled solely by a host computer.
5. The apparatus as claimed in claim 1, wherein the inspection tool’s image processing system additionally executes wafer’s front-side marking bar-code reading andor wafer identification marks reading, with consequent reading results incorporation in the information fed to data base and host.
6. The apparatus as claimed in claim 1, wherein the inspection tool incorporates auxiliary means for wafer’s-under-inspection backside marking imaging and processing means for bar-code reading andor wafer identification marks reading, with consequent reading results transfer to data base and host.
7. The apparatus as claimed in claim 2, wherein said parent tool output stage robot, or a stand alone robot’s wafer grip, is configured such that the wafer’s surface image acquisition and processing are performed in a single imaging frame.
8. The apparatus as claimed in claim 1, wherein the inspection tool’s camera focal plane centre and illumination source central point are displaced in horizontal direction relative to inspected wafer centre, in addition to their vertical displacement and rotational inclination of the preferred embodiment.
9. The apparatus as claimed in claim 1, wherein said illumination source and camera are coaxially arranged, providing for instantaneous front surface coverage in a single shot frame and minimization of the image’s perspective geometrical distortions.
10. The apparatus as claimed in claim 1, wherein the illumination source and said camera are both inclined by substantially as 30\xb0 angle at opposite directions relative a vertical, preserving the bright field imaging scheme.
11. The apparatus as claimed in claim 1, wherein the inspection tool is aimed and configured to copper CMP residues and other planarization process flaws inspection and detection.
12. The apparatus as claimed in claim 1, wherein said automatic optical inspection is capable of inspecting semiconductor production wafer’s macro defects including, lithography, bumping, back-side and edge defects, in addition to polishing residues detection.
13. A method of automatic optical self-contained inspection for pattern wafers’ polishing residue detection with sub-pixel defect size effective spatial sensitivity, based on wafer-under-inspection surface light scattering colour-intensity computerized analysis, comprising the steps of:
setting-up initial calibration and correction data derivation;
wafer image acquisition and rendering;
lighting intensity and camera sensitivity colour spectra biases and spatial variances compensation;
duple images registration and merging for full wafer surface inspection execution;
self-contained image scattering intensity analysis for outstanding, amplitude and colour-ratio comparison based, residue-covered areas discriminating against the patterned wafer area portions, not containing polishing residue defects, and
image rectification and inspection results on-screen presentation containing wafer-under-inspection zoomed image and corresponding emphasized detected residues image.
14. The method as claimed in claim 13, comprising additional steps of detected defects characterization and metrology quantitative results derivation and presentation.
15. The method as claimed in claim 13, comprising an additional step of automatic residue defects classification according to their potential harm evaluation and polishing tool malfunctioning appropriate alarm.
16. The method as claimed in claim 13, comprising an additional step of an inspection tool and its interface with a parent tool worthiness monitoring and proper worthiness-related messages generation and presentation.
17. The method as claimed in claim 13, comprising an additional step of a parent tool robot worthiness monitoring based on the wafers’ images position and its deviations analysis.
18. The method as claimed in claim 13, comprising an additional step of inter-lot and intra-lot wafers’ inspection outcome information integrative analysis for automatic inspection tools, parent tools and polishing process worthiness evaluation and malfunction prediction.
19. The method as claimed in claim 13, comprising an additional MMI step of inspection results presentation on the tool screen to allow a process operator to scroll through wafer’s lot-under-inspection or any previously inspected lot’s acquired images and residue detection results images saved in data base, for said lot’s wafers’ quality and inspection and polishing tool’s worthiness assessment.
20. The method as claimed in claim 13 implementing a calibrating step and calibration parameters derivation by means of analyzing and processing fully Tungsten covered wafer images.
21. The method as claimed in claim 20 implementing automatic, computer-driven camera parameters dynamic adjustment during calibration procedures, allowing seamless inspection tool integration and maintenance on the plentitude of parent tool specimens and amid their inter-tool manufacture tolerances and intra-tool operational variances.
22. The method as claimed in claim 13, incorporating inspection tool camera and illumination source luminance and sensitivity tolerances and dynamic changes automatic on-process compensation and worthiness assessment, by fully Tungsten covered wafer operational inspection event recognition and compensation parameters values update.
23. The method as claimed in claim 13, comprising an additional step of spatially variable residue detection threshold scheme, thus implementing CFAR and enhancing inspection sensitivity.
24. The method as claimed in claim 13, comprising an additional step of pixels basic colours’ three inter-ratios analysis method for residue’s assumed detection verification.
25. The method as claimed in claim 13, comprising an additional step of non-Tungsten polishing harmful remains detection, including pre-determined colour ratios verification quantitative criteria definitions, different from the ones used for Tungsten presence verification and based on a specific material residue scattering colour spectra.
26. The method as claimed in claim 13, comprising an additional step of silicon layer averaged thickness and its variations spatial distribution over wafer surface estimation, based on a reflected light colour spectra interference analysis.
27. The method as recited in claim 13, comprising an additional step of patterned wafers surface over-polish presence detection and quantification.
28. The method as claimed in claim 13, comprising residue-detection oriented and computationally shy algorithms for image registration.
29. The method as claimed in claim 13, comprising an additional image registration procedure step of tool-to-tool and wafer-to-wafer variable skew correction.
30. The method as claimed in claim 13, comprising an additional step of on-line data base creation, kept in the inspection tool processor storage and containing information and data pertinent for residue events post-inspection yield, polishing tools worthiness and impairment prognosis and preventive maintenance-oriented analysis.
31. The method as claimed in claim 13, comprising an additional non-operational inspection step with images retrieval from data base, instead from camera as in operational mode, allowing for inspection tool computational analysis worthiness as well as previously not encountered wafer’s scattering features investigation and inspection tool processing algorithms alternations testing.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What I claim is:
1. In a semiconductor substrate with a top surface, a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from a surface and a second region of opposite conductivity type formed into a first portion of the first region from the surface wherein the improvement comprises one edge of the first region is spaced from the edge of the second region such that the doping concentration of the first region at the surface intersection of the comers of the junction between the first and second regions is lower than it is at some other location in the first region.
2. The semiconductor substrate of claim 1 wherein the first region has a striped diffusion pattern in which adjacent stripes are close enough together that the diffusion from them extends laterally to merge to form a continuous first diffused region of variable doping concentration in planes parallel to the top surface.
3. The semiconductor substrate of claim 2 wherein the stripes have gaps located such that the maximum doping of the first region at the surface intersection of the junction between the first and second regions is lower than it is at some other part of the first region.
4. The semiconductor substrate of claim 1 further comprising a bipolar transistor wherein the collector corresponds to the first region and the base corresponds to the second region.
5. The semiconductor substrate of claim 2 further comprising a bipolar transistor wherein the collector corresponds to the first region and the base corresponds to the second region.
6. The bipolar transistor of 2 further comprising a collector contact region of first conductivity type in the collector well and outside the base and an emitter of the first conductivity type in the base in which at least one stripe of the collector well extends from under the emitter to under the collector contact.
7. The semiconductor substrate of claim 2 wherein all first region stripe mask openings are overlapped by the second region.
8. A method of simultaneously forming in one substrate PN junctions having two or more different breakdown voltages comprising the steps of:
forming at least two first regions of first conductivity type by simultaneous diffusion into a surface of a semiconductor through at least two first mask patterns;
simultaneously forming second regions of second conductivity type in the first regions having PN junctions between each second region and the first region in which it is formed, forming the mask of one of the first regions close enough to the corners of the second region which forms a PN junction with that first region that the doping of the first region at the surface intersection of the comers of the junction is lower than it is at some other point in the first region; and
forming the mask of another of the at least two first regions at a location with respect to the second region which forms a PN junction with the another first region such that the first region doping at the surface intersection of the corners of the PN junction is higher than it is at the corners of the one first region junction.
9. A method of controlling the current gain of a bipolar transistor having an emitter formed in an intrinsic base which is diffused into a semiconductor surface, an extrinsic base of higher doping than the intrinsic base formed in the intrinsic base outside the emitter, the method comprising the steps of:
forming a masked area in the intrinsic base for blocking introduction of dopants;
doping and diffusing the intrinsic base vertically and laterally such that the opposite lateral edges of the base merge in the masked area and have a lower doping there than in an unmasked area,
forming the emitter over the region of the masked area of the intrinsic base,
choosing the width of the masked area together with the doping of the intrinsic base and the emitter to yield the desired current gain.
10. A method for simultaneously forming at least two transistors having different current gains by simultaneously diffusing their bases through at least two base mask patterns and simultaneously forming emitters in the bases, the steps comprising:
forming the first base mask pattern in the base mask with a region of first width which blocks the introduction of base dopant,
forming a second base mask pattern in a second portion of the base mask to include a region of second width different from the first width which blocks the introduction of base dopant,
diffusing the base dopant vertically and laterally so that the opposite lateral edges of the base merge under the first and second masked regions in first and second bases,
simultaneously forming first and second emitters in first and second bases over first and second widths of area where base dopant introduction was blocked.
11. The method of 11 in which the width of the region in the second base mask pattern which blocks dopant introduction is zero.
12. A method of controlling the threshold voltage of an MOS transistor formed in a well including,
forming the well by introducing well dopant through a well mask into a semiconductor surface using a well mask which includes a region within the well pattern which blocks the introduction of well dopant,
diffusing the well vertically and laterally such that the lateral edges of the well merge under the region of the well pattern where well doping was blocked yielding a region of lower surface well doping than in unmasked parts of the well,
forming a gate oxide over the diffused well, and
forming a gate over the gate oxide and over the region of lower well surface doping formed by the overlapping lateral edges after the well has been diffused.
13. A semiconductor device comprising a substrate with a surface,
a P region defined by a first perimeter at the surface, extending from the surface to a first depth, and having a doping concentration that decreases with depth and with proximity to the first perimeter;
an N region defined by a second perimeter at the surface, extending from the surface to a second depth, and having a doping concentration that decreases with depth and with proximity to the second perimeter, said N region overlapping said P region;
wherein the doping concentration of the P region at the surface intersection of the P and N regions is less than the maximum doping concentration at other locations on the surface within the first perimeter where the N region overlaps the P region.
14. The semiconductor device of claim 13 wherein the regions have different maximum depths and the depth of the P region is greater than the depth of the N region.
15. A semiconductor device comprising a substrate with a surface,
an N region defined by a first perimeter at the surface, extending from the surface to a first maximum depth, and having a doping concentration that decreases with depth and with proximity to the first perimeter;
a P region defined by a second perimeter at the surface, extending from the surface to a second maximum depth, and having a doping concentration that decreases with depth and with proximity to the second perimeter, said P region overlapping said N region;
wherein the doping concentration of the N region at the surface intersection of the N and P regions is less than the maximum doping concentration at other locations on the surface within the first perimeter where the P region overlaps the N region.
16. The semiconductor device of claim 15 wherein the regions have different maximum depths and the depth of the N region is greater than the depth of the P region.
17. A method for adjusting the breakdown voltage of a PN junction comprising the steps of:
on a semiconductor substrate, forming a first mask with a first exposed region having a first perimeter;
doping the first exposed region with a dopant of a first conductivity to form a well with a first surface perimeter and with a doping concentration that decreases with the distance from the surface and with distance from the perimeter;
on the substrate and over the first region, forming a second mask with a second exposed region having a second perimeter;
doping the second exposed region with a dopant of a second conductivity opposite to the first conductivity to form a doped region with a second surface perimeter overlapping the first region and with a doping concentration that decreases with the distance from the surface and with distance from the perimeter; and
locating the perimeter of the second mask proximate to the perimeter of the first surface region so that the at the surface intersection of the junction between the two regions the concentration of the first dopant is less than the concentration at some other locations within the first perimeter that overlap the second region.
18. The method of claim 17 comprising the further step of varying the relative concentrations of the two regions to adjust the breakdown voltage of the PN junction.
19. A bipolar transistor comprising:
a semiconductor substrate having top and bottom surfaces;
a collector well diffused region in the substrate extending from the top surface into the substrate a first depth and having a first surface perimeter defined by a first length and a first width;
a base diffused region in the substrate and overlapping the collector well diffused region, said base diffused region extending from the top surface into the substrate a second depth and having a second surface perimeter defined by a second length and a second width wherein the length of the base diffused region is enclosed by the well diffused region and the width of the base diffused region is about equal to or greater than the width of the collector well diffused region; and
an emitter diffused region disposed with and surrounded by the base diffused region.
20. The bipolar transistor of claim 19 wherein the well diffused region and the base diffused region each has a doping concentration that decreases with depth and with proximity to the respective perimeters; and
wherein the doping concentration of the well diffused region at the surface intersection of the junction between the well diffused region and the corners of the base diffused region is less than the maximum doping concentration of the well diffused region at locations of the well diffused region that overlap the base diffused region.
21. The bipolar transistor of claim 19 wherein the well diffusion comprises substantially uniform doping in planes parallel to the top surface.
22. A bipolar transistor comprising:
a semiconductor substrate having top and bottom surfaces;
a collector well diffused region in the substrate extending from the top surface into the substrate variable depths and having a first surface perimeter wherein the concentration of dopant in the well diffused region comprises a first region proximate the top surface characterized by a variable concentration of doping in planes parallel to the top surface;
a base diffused region in the substrate and substantially overlapping the collector well diffused region, said base diffused region extending from the top surface into the substrate a second depth and having a second surface perimeter; and
an emitter diffused region disposed with and surrounded by the base diffused region.
23. The bipolar transistor of claim 22 wherein the collector well comprises a collector contact diffusion spaced from the base diffusion and extending from the top surface of the substrate.
24. The bipolar transistor of claim 22 further comprising a collector contact diffused region, spaced from the collector well diffused region and from the base diffused region and extending into the substrate a depth corresponding to the depth of the collector well diffused region.
25. The bipolar transistor of claim 22 further comprising a collector contact diffused region, spaced from the collector well diffused region and from the base diffused region, said collector contact diffused region extending from the top surface into the substrate a variable depths and having a contact surface perimeter wherein the concentration of dopant in the contact diffused region comprises a first region proximate the top surface characterized by a variable concentration of doping in planes parallel to the top surface.
26. A bipolar transistor comprising:
a collector region of first conductivity type having a surface;
a base of second conductivity type diffused into a portion of the collector from the surface;
the base characterized by having a region of smaller junction depth within a region of greater junction depth;
an emitter formed from the surface within the base and overlapping the region of smaller base junction depth.
27. The bipolar transistor of claim 26 further comprising a second base diffusion having a depth not substantially greater than the smaller junction depth part of the first base diffused region.
28. An MOS transistor comprising:
a substrate of semiconductor material having a top surface;
an elongated, insulated gate disposed on the top surface of the semiconductor substrate;
source and drain diffusion regions on respective opposite sides of the insulated gate; and
a well diffused region in the substrate, said well diffused region underlying the gate, source and drain and having a variable dopant concentration in regions beneath the gate.
29. The MOS transistor of claim 28 further comprising shallow source and shallow drain regions extending from the respective source and drain diffusion regions toward said gate and having a depth less than the depth of the source and drain diffusion regions.
30. A method for adjusting the breakdown voltage of a bipolar transistor comprising the steps of:
on a semiconductor substrate, forming a collector well mask with a first exposed region having a first perimeter;
doping the first exposed region with a dopant of a first conductivity to form a collector well with a first surface perimeter and with a doping concentration that decreases with the distance from the surface and with distance from the perimeter;
on the substrate and overlapping the collector well region, forming a base region mask with a second exposed region having a second perimeter;
doping the second exposed region with a dopant of a second conductivity opposite to the first conductivity to form a doped base region with a second surface perimeter overlapping the collector well region and with a doping concentration that decreases with the distance from the surface and with distance from the perimeter; and
locating the perimeter of the base region mask proximate to the perimeter of the collector well region so that the at the corners of the surface intersection of the two regions the concentration of the first dopant is less than the concentration at some other locations within the first perimeter that overlap the second region; and
masking the base doping region and doping the exposed portion of the masked base region with a first type doping to form an emitter.
31. The method of claim 30 wherein
the collector well diffused region in the substrate extends from the top surface into the substrate a first depth and has a first surface perimeter defined by a first length and a first width; and
the base diffused region in the substrate overlaps the collector well diffused region, said base diffused region extends from the top surface into the substrate a second depth and has a second surface perimeter defined by a second length and a second width wherein the length of the base diffused region is enclosed by the collector well diffused region and the width of the base diffused region is about equal to or greater than the width of the collector well diffused region.
32. A method for adjusting the breakdown voltage of a bipolar transistor comprising the steps of:
on a semiconductor substrate, forming a collector well mask comprising a series of elongated strips providing alternate exposed and covered areas of the substrate to define a collector well area;
doping the exposed portion of the substrate region with a dopant of a first conductivity to form a well with a first surface perimeter and with a doping concentration that forms a first region proximate the top surface characterized by a variable concentration of doping in planes parallel to the top surface
on the substrate and over the collector well region, forming a base region mask with a second exposed region having a second perimeter and overlapping the collector well region;
doping the base region with a dopant of a second conductivity opposite to the first conductivity to form a doped base region with a second surface perimeter overlapping the collector well region and having a doping concentration that decreases with the distance from the surface and with distance from the perimeter; and
masking the base doping region and doping the exposed portion of the masked base region with a first type doping to form an emitter.
33. The method of claim 32 further comprising the step of forming a collector contact diffusion spaced from the base diffusion and extending to the bottom of the collector well.
34. The method of claim 33 further comprising the step of spacing the location of the collector contact diffusion from the collector well diffusion.
35. The method of claim 34 further comprising the step of:
forming the collector contact diffusion by masking the substrate with a series of elongated strips to provide alternate exposed and covered areas of the substrate to define a collector contact diffusion area; and
doping the exposed areas with the first dopant of the collector well diffusion.
36. The method of claim 35 wherein the collector well and the collector contact diffusions are simultaneously formed.
37. A method for adjusting the breakdown voltage of a bipolar transistor comprising the steps of:
on a semiconductor substrate, forming a collector well mask comprising a series of elongated strips providing alternate exposed and covered areas of the substrate to define a collector well area;
doping the exposed portion of the substrate region with a dopant of a first conductivity to form a well with a first surface perimeter and with a doping concentration that forms a collector well region of substantially constant concentration of doping in planes parallel to the top surface;
on the substrate and over the collector well region, forming a base region mask with a second exposed region having a second perimeter and overlapping the collector well region;
doping the base region with a dopant of a second conductivity opposite to the first conductivity to form a doped base region with a second surface perimeter overlapping the collector well region and having a variable concentration of doping in planes parallel to the top surface;
masking the base doping region and doping the exposed portion of the masked base region with a first type doping to form an emitter.
38. A method of forming a bipolar transistor having selected electrical parameters including:
forming the base by diffusion through a mask opening which includes a masked strip within the opening;
diffusing the base vertically and laterally through the mask such that the laterally diffused edges of the base merge in the region under the masked strip forming a portion of base there which has a shallower junction with the collector and lower integrated doping than it does in the unmasked region; and
forming an emitter which overlaps the portion of base formed under the masked strip.
39. A method of forming a bipolar transistor further comprising the step of masking the base well a second time and doping the exposed region with a base dopant to form a second, shallow base region with a depth less the first base depth.
40. A method of forming an MOS transistor comprising the steps of:
forming a mask on a top surface of a semiconductor substrate defining a perimeter of an exposed well area with an elongated mask stripe within the area over a gate region;
doping the exposed areas on the opposite sides of the elongated mask strip;
removing the mask stripe;
forming an insulted gate over the region where the strip was located; and
forming a source and a drain on opposite sides of the insulated gate.
41. The method of claim 40 wherein the doping in the well has a variable concentration of doping in planes parallel to the top surface.
42. The method of claim 41 further comprising the step of forming doped source and doped drain extension regions proximate the respective source and drain regions an extending from the respective source and drain toward the gate.