1. A method of adapting a rate of an output signal to a rate of an output medium, said method comprising:
providing a media access controller comprising an internal clock;
inputting an external clock signal into said media access controller;
providing a register at an output of said media access controller for outputting data to an external device, said register comprising a first input configured to control an output of the register and a second input configured to control an input to said register;
providing said external clock signal to said first input of said register;
providing an internal clock signal from said internal clock to said second input of said register;
measuring a capacity of said register; and
substituting said internal clock signal with said external clock signal when said capacity reaches a predetermined level such that said external clock signal is provided to both said first input and said second input of said register.
2. The method of claim 1, further comprising continuing said internal clock signal when said capacity falls below said predetermined level such that said internal clock signal is provided to said second input of said register and said external clock signal is provided to said first input of said register.
3. The method of claim 1, wherein providing a register comprises providing a FIFO as said register.
4. The method of claim 1, wherein inputting an external clock signal comprises matching said external clock with a speed of said external device.
5. The method of claim 1, further comprising matching the internal clock to match said external clock.
6. An apparatus to adapt a rate of an output signal to a rate of an output medium, said apparatus comprising:
a register configured to output data to an external device, said register comprising a first input configured to control an output of the register and a second input configured to control an input to said register;
a receiver configured to accept a signal from an external clock over the output medium and to provide said external clock signal to said first input of said register; and
an internal clock configured to provide an internal clock signal from said internal clock to said second input of said register,
wherein said register is further configured to measure a capacity of said register, and
substitute said internal clock signal with said external clock signal when said capacity reaches a predetermined level such that said external clock signal is provided to both to said first input and to said second input of said register.
7. The apparatus of claim 6, wherein said register is further configured to use said internal clock signal when said capacity falls below said predetermined level such that said internal clock signal is provided to said second input of said register and said external clock signal is provided to said first input of said register.
8. The apparatus of claim 6, wherein said register comprises a FIFO.
9. The apparatus of claim 6, wherein said external clock is matched to a speed of said external device.
10. The apparatus of claim 6, wherein internal clock is further configured to:
receive said external clock signal, and
match said external clock.
11. An apparatus for adapting a rate of an output signal to a rate of an output medium, said apparatus comprising:
register means for outputting data to an external device, said register means comprising first input means for controlling an output of the register and second input means for controlling an input to said register;
receiver means for accepting a signal from an external clock means over the output medium and for providing said external clock signal to said first input means of said register means; and
an internal clock means for providing an internal clock signal from said internal clock to said second input of said register,
wherein said register means is further configured to measure a capacity of said register means and to substitute said internal clock signal with said external clock signal when said capacity reaches a predetermined level such that said external clock signal is provided to both said first input means and said second input means of said register means.
12. The apparatus of claim 11, wherein said register means is further configured to use said internal clock signal when said capacity falls below said predetermined level such that said internal clock signal is provided to said second input means of said register means and said external clock signal is provided to said first input means of said register means.
13. The apparatus of recited in claim 11, wherein said register means comprises a FIFO.
14. The apparatus of recited in claim 11, wherein said external clock means is matched to a speed of said external device.
15. The apparatus of recited in claim 11, wherein internal clock means is further configured to receive said external clock signal, and match said external clock.
16. A computer readable medium having recorded and stored thereon instructions for adapting a rate of an output signal to a rate of an output medium that, when executed, perform the actions of:
providing a media access controller comprising an internal clock;
inputting an external clock signal into said media access controller;
providing a register at an output of said media access controller for outputting data to an external device, said register comprising a first input configured to control an output of the register and a second input configured to control an input to said register;
providing said external clock signal to said first input of said register;
providing an internal clock signal from said internal clock to said second input of said register;
measuring a capacity of said register; and
substituting said internal clock signal with said external clock signal when said capacity reaches a predetermined level such that said external clock signal is provided to both said first input and said second input of said register.
17. The computer readable medium of claim 16 further comprising instructions that, when executed, perform the actions of continuing said internal clock signal when said capacity falls below said predetermined level such that said internal clock signal is provided to said second input of said register and said external clock signal is provided to said first input of said register.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multi-layer device comprising:
a substrate;
at least one electrical component located on the substrate;
an electrically conductive bond layer, formed on the substrate and surrounding the electrical component; and
an encasing layer, wherein the encasing layer is bonded to the bond layer to form a sealed cavity encasing the electrical component therein.
2. A device according to claim 1, wherein the encasing layer is anodically bonded to the bond layer to form the sealed cavity.
3. A device according to claim 1, wherein the substrate comprises an electrical conductor, positioned in isolation from the surface provided to receive the bond layer, to connect the component with an external contact pad.
4. A device according to claim 3, wherein the conductor is formed from at least one conducting layer coupled with conducting plugs.
5. A device according to claim 4, wherein the conducting layer is surrounded by dielectric layers.
6. A device according to claim 1, wherein the component is CMOS or BiCMOS circuitry.
7. A device according to claim 1, wherein the component is a pressure sensor or an inertial sensor.
8. A device according to claim 1, further comprising a conductive shielding layer which is placed on the glass wafer and connected to the substrate, in order to protect the device from the electric field generated during anodic bonding.
9. A device according to claim 1, wherein a second encasing layer is bonded to a second surface of the substrate to form a second sealed cavity.
10. A multi-layer device comprising:
a substrate including a support region;
at least one electrical component located within the support region;
an electrically conductive layer surrounding the support region; and
an encasing layer including a cavity,
wherein the electrically conductive layer is configured to bond the encasing layer to the substrate such that the at least one electrical component is sealed within the cavity.