1. A semiconductor structure comprising:
a substrate comprising a first bond pad;
a passivation layer overlying the substrate and at least a portion of the first bond pad;
a first under bump metal (UBM) layer disposed over the first bond pad and extending through the passivation layer to the first bond pad, the first UBM layer having a center portion and extensions extending from the center portion over a top surface of the passivation layer; and
a conductive bump over the center portion of the UBM layer such that at least a portion of the extensions protrude from an edge of the conductive bump.
2. The semiconductor structure of claim 1, wherein the conductive bump extends out over at least a portion of the extensions.
3. The semiconductor structure of claim 1, wherein the substrate further comprises a second bond pad and further comprising a second UBM layer disposed over the second bond pad and extending through the passivation layer to the second bond pad, the second UBM layer having a center portion and extensions extending from the center portion over the top surface of the passivation layer.
4. The semiconductor structure of claim 3, wherein the first bond pad and the second bond pad are adjacent bond pads, and wherein the extensions of the first UBM layer are rotated relative to the extensions of the second UBM layer.
5. The semiconductor structure of claim 3, wherein the first bond pad and the second bond pad are adjacent bond pads, and wherein the extensions of the first UBM layer are aligned with the extensions of the second UBM layer.
6. The semiconductor structure of claim 1, wherein the extensions have a shape of a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface.
7. A semiconductor structure comprising:
a substrate having a plurality of bond pads;
a passivation layer over the substrate, the passivation layer having an opening over each of the plurality of bond pads; and
a plurality of under bump metal (UBM) structures, each of the plurality of UBM structures being over a corresponding one of the openings, each of the plurality of UBM structures having a center portion and a plurality of extensions protruding from the center portion, the plurality of extensions being over the passivation layer.
8. The semiconductor structure of claim 7, further comprising a conductive bump over the center portion of the UBM structures such that at least a portion of the extensions protrude from an edge of the conductive bump.
9. The semiconductor structure of claim 8, wherein the conductive bump extends out over at least a portion of the extensions.
10. The semiconductor structure of claim 7, wherein the extensions of adjacent UBM structures are rotated relative to each other.
11. The semiconductor structure of claim 7, wherein the extensions of adjacent UBM structures are aligned with each other.
12. The semiconductor structure of claim 7, wherein the extensions have a shape of a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a first insulating layer;
a semiconductor layer provided on the first insulating layer;
a first semiconductor region selectively provided in the semiconductor layer;
a second semiconductor region selectively provided in the semiconductor layer, spaced from the first semiconductor region, and having a conductivity type opposite to a conductivity type of the first semiconductor region;
a third semiconductor region provided in the semiconductor layer, being in contact with the first semiconductor region, and having a conductivity type opposite to a conductivity type of the first semiconductor region;
a fourth semiconductor region provided in the semiconductor layer, being in contact with the second semiconductor region, and having a conductivity type opposite to a conductivity type of the second semiconductor region;
a first main electrode provided in contact with the first semiconductor region and the third semiconductor region;
a second main electrode provided in contact with the second semiconductor region;
a second insulating layer provided on the semiconductor layer;
a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and
a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer,
the first conductive material including a control electrode portion provided above the third semiconductor region and a field plate portion, one end of the field plate portion being connected to the control electrode portion, and the other end being connected to the second main electrode, and
the second conductive material including a first portion provided in a first trench passing through a portion of the third semiconductor region opposed to the control electrode portion and reaching the first insulating layer.
2. The device according to claim 1, wherein the second conductive material includes a second portion provided in a second trench passing through a portion of the semiconductor layer opposed to the field plate portion and reaching the first insulating layer.
3. The device according to claim 1, wherein a bottom of the first portion of the second conductive material is located on a side of the first insulating layer of a boundary surface between the semiconductor layer and the first insulating layer.
4. The device according to claim 2, wherein a bottom of the second portion of the second conductive material is located on a side of the first insulating layer of a boundary surface between the semiconductor layer and the first insulating layer.
5. The device according to claim 2, wherein the first conductive material is formed in a spiral planar pattern.
6. The device according to claim 5, wherein a plurality of the second trenches and a plurality of the second portions of the second conductive material are provided intermittently along a spirally extending direction of the first conductive material.
7. The device according to claim 1, wherein the field plate portion is made of a material having a higher resistance than those of the first main electrode and the second main electrode.
8. The device according to claim 1, further comprising an insulating film provided between the semiconductor layer and the second conductive material.
9. A semiconductor device comprising:
a first insulating layer;
a semiconductor layer provided on the first insulating layer;
a first semiconductor region selectively provided in the semiconductor layer;
a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region;
a third semiconductor region provided in the semiconductor layer, being in contact with the first semiconductor region, and having a conductivity type opposite to a conductivity type of the first semiconductor region;
a first main electrode provided in contact with the first semiconductor region and the third semiconductor region;
a second main electrode provided in contact with the second semiconductor region;
a second insulating layer provided on the semiconductor layer;
a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and
a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer,
the first conductive material including a control electrode portion provided above the third semiconductor region and a field plate portion, one end of the field plate portion being connected to the control electrode portion, and
the second conductive material including a first portion and a second portion, the first portion being provided in a first trench passing through a portion of the third semiconductor region opposed to the control electrode portion and reaching the first insulating layer, the second portion being provided in a second trench passing through a portion of the semiconductor layer opposed to the field plate portion and reaching the first insulating layer.
10. The device according to claim 9, wherein the other end of the field plate portion is connected to the second main electrode via a switch.
11. The device according to claim 9, further comprising an insulating film provided between the semiconductor layer and the second conductive material.
12. A semiconductor device comprising:
a first insulating layer;
a semiconductor layer provided on the first insulating layer;
a first semiconductor region selectively provided in the semiconductor layer;
a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region;
a third semiconductor region provided between the first semiconductor region and the second semiconductor region in the semiconductor layer, being in contact with the first semiconductor region, and having a conductivity type opposite to a conductivity type of the first semiconductor region;
a fourth semiconductor region provided in the semiconductor layer, being in contact with the first semiconductor region and the third semiconductor region, and having a higher impurity concentration than an impurity concentration of the third semiconductor region;
a first main electrode provided in contact with the first semiconductor region and the fourth semiconductor region;
a second main electrode provided in contact with the second semiconductor region;
a second insulating layer provided on the semiconductor layer;
a control electrode portion provided in the second insulating layer above the third semiconductor region; and
a conductive material provided in a trench passing through a portion of the third semiconductor region opposed to the control electrode portion and reaching the first insulating layer, the conductive material being in contact with the control electrode portion.
13. The device according to claim 12, further comprising an insulating film provided between the semiconductor layer and the conductive material.