1. An electric carpet seaming tape iron, comprising:
a base plate,
a housing secured to the base plate and having a handle,
a first heating element secured to the base plate and contained in the housing,
a second heating element secured to the base plate and contained in the housing,
a power cord supplying electric power to the iron and connected into the housing,
a first circuit connected to power from the power cord and connecting power to the first heating element at all times when the iron is in an \u201con\u201d condition for use, and
a second circuit connected to power from the power cord and including a temperature control means for cycling the second heating element on and off in response to sensed temperature of the iron’s base plate, as needed to maintain a desired range of temperature of the base plate during the iron’s \u201con\u201d condition.
2. The apparatus of claim 1, wherein the temperature control means comprises a mechanical thermostat in the second circuit.
3. The apparatus of claim 1, wherein the temperature control means comprises a non-mechanical temperature control in the second circuit.
4. The apparatus of claim 1, wherein the first heating element has a power draw of approximately 150 watts.
5. The apparatus of claim 4, wherein the second heating element has a power draw of approximately 350 watts.
6. The apparatus of claim 1, wherein the first heating element is of power draw sufficient to hold the iron’s base plate at a temperature of about 300\xb0 F. to 390\xb0 F. when the iron is \u201con\u201d but not being used.
7. The apparatus of claim 1, wherein the temperature control means comprises a mechanical thermostat, and wherein the iron exhibits a temperature oscillation of less than 40\xb0 F. in use.
8. The apparatus of claim 1, wherein the first and second heating elements are contained within a single heating element jacket.
9. The apparatus of claim 1, wherein the second circuit includes a diode and switching means for powering the second heating element selectively at zero power, one-half power or full power as needed to maintain desired temperature, thereby providing additional power combinations from the first and second heating elements.
10. The apparatus of claim 10, wherein the first circuit also includes a diode and first circuit switching means, for maintaining the first heating element at least at one-half power at all times when the iron is in the \u201con\u201d condition and for selectively powering the first heating element at full power, whereby further combinations of power settings of the first and second heating elements are possible, permitting smaller increments of power levels to the heating elements.
11. The apparatus of claim 10, wherein the first heating element has a power capacity of 150 watts, and the second heating element has a power capacity of 400 watts.
12. The apparatus of claim 1, wherein the iron is about three inches in width.
13. The apparatus of claim 1, wherein the iron is about six inches in width.
14. An electric carpet seaming tape iron, comprising:
a base plate,
a housing secured to the base plate and having a handle,
a first heating element secured to the base plate and contained in the housing,
a second heating element secured to the base plate and contained in the housing,
a power cord supplying electric power to the iron and connected into the housing,
a first circuit connected to power from the power cord and connecting power at a base level to the first heating element at all times when the iron is in an \u201con\u201d condition for use,
a second circuit connected to power from the power cord and including a diode and second circuit switching means providing for powering the second heating element at either zero power, one-half power or full power, and
temperature control means connected to the second circuit switching means, for cycling the second heating element on and off, at one-half power or full power, in response to sensed temperature of the iron’s base plate, as needed to maintain in combination with the first heating element a desired range of temperature of the base plate during the iron’s \u201con\u201d condition.
15. The apparatus of claim 15, wherein the first circuit also includes a diode and first circuit switching means, for maintaining the first heating element at least at one-half power at all times when the iron is in the \u201con\u201d condition and for selectively powering the first heating element at full power, whereby further combinations of power settings of the first and second heating elements are possible, permitting smaller increments of power levels to the heating elements.
16. The apparatus of claim 16, wherein the first heating element has a power capacity of 200 watts, and the second heating element has a power capacity of 400 watts.
17. The apparatus of claim 15, wherein the first heating element has a power capacity of 150 watts, and the second heating element has a power capacity of 400 watts.
18. The apparatus of claim 15, wherein the first and second heating elements are contained within a single heating element jacket.
19. The apparatus of claim 15, wherein the iron is about three inches in width.
20. The apparatus of claim 15, wherein the iron is about six inches in width.
21. An electric carpet seaming tape iron, comprising:
a base plate,
a housing secured to the base plate and having a handle,
a heating element secured to the base plate and contained in the housing,
a power cord supplying electric power to the iron and connected to the housing,
a circuit connected to power from the power cord and including a diode and circuit switching means providing for powering the heating element at one-half power or full power, and
temperature control means connected to the circuit switching means, for cycling the heating element on at half power or full power, in response to sensed temperature of the iron’s base plate, as needed to maintain a desired range of temperature of the base plate during the iron’s \u201con\u201d condition.
22. The apparatus of claim 22, wherein the temperature control means includes means for switching off all power to the heater element, so that to maintain a desired minimum temperature when the iron is idle, one-half power to the heater element can be cycled on and off as needed, and during active use of the iron, power to the heating element can be switched between one-half power and full power.
23. The apparatus of claim 1, wherein the second circuit includes switching means for powering the second heating element selectively at zero power, one-half power or full power as needed to maintain desired temperature, thereby providing additional power combinations from the first and second heating elements.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A limited switch dynamic logic circuit comprising:
a dynamic node;
precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal;
a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal;
static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output; and
a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper output reinforces a first logic state of said dynamic node and does not reinforce a second logic state of said dynamic node in response to logic states of said first and second supply signals.
2. The limited switch dynamic logic circuit of claim 1 further comprising a first logic gate having a first mode input coupled to a first mode signal and a first mode output coupled to said first supply terminal and generating said first supply signal, wherein said first supply signal has said first logic state when said first mode signal has said second logic state and said first supply signal has said second logic state when said first mode signal has said first logic state.
3. The limited switch dynamic logic circuit of claim 1 further comprising a second logic gate having a second mode input coupled to a second mode signal, a third mode input coupled to said first mode signal and a second mode output coupled to said second supply terminal and generating said second supply signal, wherein said second supply signal has said first logic state when said second mode signal has said second logic state and said third mode output has said second logic state and said second supply signal has said second logic state when either said first or second mode signal has said first logic state.
4. The limited switch dynamic logic circuit of claim 2, wherein said first logic gate is an inverter logic gate.
5. The limited switch dynamic logic circuit of claim 3, wherein said second logic gate is a NOR logic gate.
6. The limited switch dynamic logic circuit of claim 1, wherein said keeper circuit comprises:
an inverter having an input coupled to said dynamic node, an inverter output, a positive power supply input coupled to said first supply terminal, and a second power supply input coupled to said second supply terminal; and
an electronic switch having an input coupled to said inverter output, a first terminal coupled to said positive power supply voltage and a second terminal coupled to said dynamic node, wherein said electronic switch couples said positive power supply voltage to said dynamic node when said inverter output has said first logic state and is OFF when said inverter output has said second logic state.
7. The limited switch dynamic logic circuit of claim 6, wherein said inverter comprises:
a first P channel field effect transistor (PFET) having a drain terminal coupled to said positive power supply input, a source terminal, and a gate terminal coupled to said dynamic node; and
a first N channel field effect transistor (NFET) having a drain terminal coupled to said source terminal of said first PFET, a gate terminal coupled to said dynamic node, and a source terminal coupled to said negative power supply input.
8. The limited switch dynamic logic circuit of claim 7, wherein said electronic switch comprises a second PFET having a gate terminal coupled to said inverter output, a source terminal coupled to said positive power supply voltage and a drain terminal coupled to said dynamic node.
9. The limited switch dynamic logic circuit of claim 2, wherein said first mode signal is a burn-in mode signal having said first logic state when a burn-in mode is disabled and said second logic state when said burn-in mode is enabled.
10. The limited switch dynamic logic circuit of claim 2, wherein said second mode signal is a slow_mode signal setting a fifty percent duty cycle clock mode, wherein said slow_mode signal enables a fifty percent duty cycle clock when said slow_mode signal has said second logic state and enables a pulse clock when said slow_mode signal has said first logic state.
11. A logic device comprising:
a plurality of limited switch dynamic logic (LSDL) circuits wherein each of said LSDL circuits has a dynamic node, precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal, a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal, static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output, and a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper output reinforces a first logic state of said dynamic node and does not reinforce a second logic state of said dynamic node in response to logic states of said first and second supply signals.
12. The logic device of claim 11 further comprising a first logic gate having a first mode input coupled to a first mode signal and a first mode output coupled to said first supply terminal and generating said first supply signal, wherein said first supply signal has said first logic state when said first mode signal has said second logic state and said first supply signal has said second logic state when said first mode signal has said first logic state.
13. The logic device of claim 11 further comprising a second logic gate having a second mode input coupled to a second mode signal, a third mode input coupled to said first mode signal and a second mode output coupled to said second supply terminal and generating said second supply signal, wherein said second supply signal has said first logic state when said second mode signal has said second logic state and said third mode output has said second logic state and said second supply signal has said second logic state when either said first or second mode signal has said first logic state.
14. The logic device of claim 11, wherein said keeper circuit comprises:
an inverter having an input coupled to said dynamic node, an inverter output, a positive power supply input coupled to said first supply terminal, and a second power supply input coupled to said second supply terminal; and
an electronic switch having an input coupled to said inverter output, a first terminal coupled to said positive power supply voltage and a second terminal coupled to said dynamic node, wherein said electronic switch couples said positive power supply voltage to said dynamic node when said inverter output has said first logic state and is OFF when said inverter output has said second logic state.
15. The logic device of claim 12, wherein said first mode signal is a burn-in mode signal having said first logic state when a burn-in mode is disabled and said second logic state when said burn-in mode is enabled.
16. The logic device of claim 12, wherein said second mode signal is a slow_mode signal setting a fifty percent duty cycle clock mode, wherein said slow_mode signal enables a fifty percent duty cycle clock when said slow_mode signal has said second logic state and enables a pulse clock when said slow_mode signal has said first logic state.
17. A data processing system comprising:
a central processing unit (CPU); and
a memory operable for communicating instructions and operand data to said CPU, wherein said CPU includes a logic system having a logic device, said logic device including a plurality of limited switch dynamic logic (LSDL) circuits wherein each of said LSDL circuits has a dynamic node, precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal, a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal, static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output, and a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper output reinforces a first logic state of said dynamic node and does not reinforce a second logic state of said dynamic node in response to logic states of said first and second supply signals.
18. The data processing system of claim 17 further comprising a first logic gate having a first mode input coupled to a first mode signal and a first mode output coupled to said first supply terminal, wherein said first mode output has said first logic state when said first mode signal has said second logic state and said first mode output has said second logic state when said first mode signal has said first logic state.
19. The data processing system of claim 17 further comprising a second logic gate having a second mode input coupled to a second mode signal, a third mode input coupled to said first mode signal and a second mode output coupled to said second supply terminal, wherein said second mode output has said first logic state when said second mode signal has said second logic state and said third mode output has said second logic state and said second mode output has said second logic state when either said first or second mode signal has said first logic state.
20. The data processing system of claim 17, wherein said keeper circuit comprises:
an inverter having an input coupled to said dynamic node, an inverter output, a positive power supply input coupled to said first supply terminal, and a second power supply input coupled to said second supply terminal; and
an electronic switch having an input coupled to said inverter output, a first terminal coupled to said positive power supply voltage and a second terminal coupled to said dynamic node, wherein said electronic switch couples said positive power supply voltage to said dynamic node when said inverter output has said first logic state and is OFF when said inverter output has said second logic state.
21. A limited switch dynamic logic circuit comprising:
a dynamic node;
precharge circuitry coupled to said dynamic for precharging the dynamic node to a logic one during a precharge cycle of a clock signal;
a logic tree coupled to said dynamic node for evaluating said dynamic node to a logic one or a logic zero in response to combinations of logic states of plurality of logic inputs coupled to said logic tree during an evaluation cycle of said clock signal;
static logic circuitry for latching a logic state of said dynamic node and holding said logic state during said precharge cycle of said clock signal, wherein said static logic circuitry generates said output and said complementary output; and
a keeper circuit having a keeper input coupled to said dynamic node, a keeper output coupled to said dynamic node, a first supply terminal coupled to a first supply signal, and a second supply terminal coupled to a second supply signal, wherein said keeper circuit is selectively enabled during a burn-in mode and a slow clock mode by logic states of said first and second supply signals.