1. A method of forming a capacitor, comprising:
forming a bottom electrode layer that includes tungsten;
forming a tungsten oxide buffer layer overlying the bottom electrode layer, including annealing the tungsten oxide buffer layer at a temperature of at least 700 degrees Celsius to form an orthorhombic crystal structure;
forming a dielectric layer directly on the tungsten oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
2. The method of claim 1, further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
3. The method of claim 1, wherein the method is performed in the order presented.
4. A method of forming a capacitor, comprising:
forming a bottom electrode layer, including tungsten, on a substrate;
oxidizing the bottom electrode layer to form a tungsten oxide buffer layer overlying the bottom electrode layer, and annealing the tungsten oxide buffer layer at a temperature of at least 700 degrees Celsius;
forming an orthorhombic crystal structure;
forming a dielectric layer directly on the tungsten oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
5. The method of claim 4, wherein the method is performed in the order presented.
6. A method of forming a capacitor, comprising:
forming a bottom electrode layer, which includes tungsten, on a substrate;
oxidizing the bottom electrode layer to form a tungsten oxide buffer layer overlying the bottom electrode layer;
annealing the tungsten oxide buffer layer at a temperature of about 750 degrees Celsius, wherein the annealing includes converting the tungsten oxide buffer layer to an orthorhombic crystal structure;
forming a dielectric layer directly on the tungsten oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
7. The method of claim 6, wherein the method is performed in the order presented.
8. The method of claim 7, wherein the bottom electrode is deposited by chemical vapor deposition, and the top electrode is deposited by chemical vapor deposition.
9. The method of claim 6, wherein the dielectric layer is formed to a thickness of about 80 \u212b.
10. A method of forming a capacitor, comprising:
forming a bottom electrode layer, which includes tungsten, on a substrate;
oxidizing the bottom electrode layer to form a metal oxide buffer layer overlying the bottom electrode layer;
annealing the buffer layer at about 700 degrees Celsius;
converting a monoclinic crystalline structure to an orthorhombic crystalline structure;
forming a dielectric layer directly on the metal oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
11. The method of claim 10, wherein the buffer layer is annealed for about one minute.
12. The method of claim 10, wherein the buffer layer is annealed in an N2 ambient.
13. A method of forming a capacitor, comprising:
forming a first electrode layer;
forming a second electrode layer, wherein at least one of the first electrode layer and the second electrode layer includes tungsten;
forming a dielectric layer interposed between the first electrode layer and the second electrode layer; and
forming a tungsten oxide buffer layer in direct contact with the dielectric layer and one of the first and second electrode layers, and annealing the tungsten oxide buffer layer at a temperature of at least 700 degrees Celsius and including forming an orthorhombic crystal lattice from a monoclinic crystal lattice.
14. The method of claim 13, wherein forming the tungsten oxide buffer layer includes oxidizing the one of the first and second electrode layers to form the tungsten oxide buffer layer before annealing the tungsten oxide buffer layer.
15. A method of forming a capacitor, comprising:
forming a bottom electrode layer;
forming an orthorhombic crystal structured buffer layer overlying the bottom electrode layer and wherein forming the orthorhombic crystal structured buffer layer includes annealing at a temperature greater than 700 degrees C;
forming a dielectric layer overlying the buffer layer; and
forming a top electrode layer overlying the dielectric layer.
16. The method of claim 15, further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
17. The method of claim 15, wherein the method is performed in the order presented.
18. A method of forming a capacitor, comprising:
forming a bottom electrode layer;
forming a metal oxide buffer layer overlying the bottom electrode layer;
annealing the metal oxide buffer layer at a temperature of at least 700 degrees C, wherein annealing includes forming at least a portion of an orthorhombic crystal structure;
forming a single compound, dielectric layer directly on the buffer layer, the dielectric layer having a dielectric constant less than a dielectric constant of the buffer layer; and
forming a top electrode layer overlying the dielectric layer.
19. The method of claim 18, further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
20. The method of claim 18, wherein the method is performed in the order presented.
21. A method of forming a capacitor, comprising:
forming a bottom electrode layer;
annealing the bottom electrode layer;
forming a metal oxide buffer layer overlying the bottom electrode layer;
annealing the buffer layer at a temperature of at least 700 degrees Celsius;
converting a monoclinic crystal lattice to an orthorhombic crystal structure;
forming a dielectric layer directly on the metal oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer.
22. The method of claim 21, further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
23. The method of claim 22, wherein the method is performed in the order presented.
24. A method of forming a capacitor, comprising:
forming a bottom electrode layer that includes tungsten;
forming a tungsten oxide buffer layer overlying the bottom electrode layer, wherein the forming includes placing the dielectric layer in an inert gas heated to at least 700 degrees Celsius, and wherein the tungsten oxide buffer layer includes at least a portion of a monoclinic crystal lattice;
converting the at least a portion of monoclinic crystal lattice to at least a portion of an orthorhombic crystal structure;
forming a dielectric layer directly on the tungsten oxide buffer layer; and
forming a top electrode layer overlying the dielectric layer, wherein forming a dielectric layer includes depositing a Ta2O5 layer.
25. The method of claim 1, wherein forming the bottom electrode layer comprises forming a layer of tungsten nitride.
26. The method of claim 10, wherein forming the bottom electrode layer comprises forming a layer of tungsten nitride; and wherein oxidizing the bottom electrode layer includes forming a tungsten oxide layer.
27. The method of claim 26, wherein forming a dielectric layer includes depositing a Ta2O5 layer.
28. The method of claim 15, wherein forming a bottom electrode layer includes forming a tungsten nitride bottom electrode layer, and wherein forming a buffer layer includes oxidizing the tungsten nitride bottom electrode layer to form a tungsten trioxide buffer layer.
29. The method of claim 18, wherein forming a dielectric layer includes depositing a Ta2O5 layer, wherein forming a bottom electrode layer includes forming a tungsten nitride bottom electrode layer, and wherein forming a metal oxide buffer layer includes oxidizing the tungsten nitride bottom electrode layer to form a tungsten trioxide buffer layer.
30. A method of forming a capacitor, comprising:
forming a bottom electrode layer, the bottom electrode layer including a metal material;
forming a buffer layer directly contacting the bottom electrode layer, the buffer layer including a metal oxide material, and the buffer layer having orthorhombic crystal structure;
annealing the buffer layer at about 700 degrees Celsius, wherein annealing includes changing the crystal lattice from a monoclinic crystalline form to an orthorhombic crystalline form;
forming a dielectric layer directly contacting the buffer layer, and the dielectric layer having a dielectric constant less than a dielectric constant of the buffer layer; and
forming a top electrode layer directly contacting the dielectric layer.
31. A method of forming a capacitor, comprising:
forming a bottom electrode layer, the bottom electrode including tungsten;
forming a buffer layer directly contacting the bottom electrode layer, the buffer layer including tungsten oxide;
annealing the buffer layer in an N2 ambient at a temperature of at least 700 degrees Celsius;
changing a monoclinic crystalline structure to an orthorhombic crystalline form;
forming a dielectric layer directly contacting the buffer layer, and the dielectric layer having a dielectric constant less than a dielectric constant of the buffer layer; and
forming a top electrode layer directly contacting the dielectric layer.
32. The method of claim 1, wherein forming a tungsten oxide buffer layer includes forming a buffer layer having a leakage current less than 100\xd710\u221215 Amperes per capacitive cell.
33. The method of claim 1, wherein forming a tungsten oxide buffer layer includes forming a buffer layer having a capacitance greater than 7\xd710\u221215 Farads per capacitive cell.
34. The method of claim 1, wherein forming a bottom electrode includes forming a bottom electrode tat is about 5 times the thickness of the dielectric layer.
35. The method of claim 1, wherein forming a bottom electrode layer includes forming a bottom electrode comprising WNn with 0<n<=6.
36. The method of claim 1, wherein forming a bottom electrode layer includes forming a bottom electrode comprising W2N.
37. The method of claim 4, wherein forming an orthorhombic crystal structure includes forming an orthorhombic crystal structure having a leakage current less than 100\xd710\u221215 Amperes per capacitor.
38. The method of claim 36, wherein forming an orthorhombic crystal structure includes forming an orthorhombic crystal structure having a capacitance of at least 7\xd710\u221215 Farads per capacitor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory tag comprising a resonant circuit part and a non-volatile memory,
the resonant circuit part being operable, in response to a reader signal received from a reader, to provide power to the memory,
the tag being operable to read the memory and transmit data stored in the memory in response to the signal from the reader,
wherein the data is stored in the memory in a plurality of data units, each data unit having an associated sequence number,
the tag being operable to store the sequence number of the data unit to be transmitted in a register in the non-volatile memory,
when power is supplied to the memory, the data units are transmitted in a first incremental sequence, the first data unit to be transmitted depending on the stored sequence number, and
wherein, when power is initially supplied to the memory, the stored sequence number is decremented and thereafter the data units are transmitted in the first sequence until power is removed from the memory, such that at least one data unit that was previously transmitted is retransmitted.
2. A memory tag according to claim 1 operable to transmit the data unit in a packet comprising validity information.
3. A memory tag according to claim 2 wherein the validity information comprises cyclic redundancy check data.
4. A memory tag according to claim 2 wherein the packet further comprises the sequence number of the data unit.
5. A memory tag according to claim 1 operable to read the stored sequence number, read the data unit associated with the stored sequence number, transmit the data unit and increment the stored sequence number.
6. A method of operating a memory tag to transmit stored data, wherein the data comprises a plurality of data units each having an associated sequence number,
the method comprising the steps of
determining a first data unit to be transmitted in accordance with a stored sequence number and transmitting the data units in incremental sequence beginning with the first data unit; and
when power is removed and re-supplied to the memory tag, again determining a data unit by retrieving the stored sequence number and decrementing it.
7. A method according to claim 6 further comprising repeating the steps of;
reading a register,
reading the data unit associated with the stored sequence number and transmitting the data unit, and
incrementing the sequence number stored in the register.
8. A method according to claim 6 wherein the step of retrieving the stored sequence number and decrementing it comprises decrementing the sequence number stored in the register.
9. A method according to claim 8 comprising transmitting validation information with the data unit.
10. A memory tag comprising a resonant circuit part and a non-volatile memory,
the resonant circuit part being operable, in response to a reader signal received from a reader, to provide power to the memory,
the tag being operable to read the memory and transmit data stored in the memory in response to the signal from the reader,
wherein the data is stored in the memory in a plurality of data units, each data unit having an associated sequence number,
the memory tag being operable to store the sequence number of the data unit to be transmitted in a register in the non-volatile memory, and
when power is initially supplied to the memory, the memory tag is operable to;
decrementing the sequence number stored in a non-volatile memory of the memory tag to produce a changed sequence number, determine a first data unit to be transmitted in accordance with the changed sequence number, read the first data unit and transmit the first data unit,
and repeat steps of:
reading the stored sequence number,
reading the data unit associated with the stored sequence number and transmitting the data unit, and
incrementing the stored sequence number in the register.
11. A memory tag comprising a resonant circuit part and a non-volatile memory,
the resonant circuit part being operable, in response to a reader signal received from a reader, to provide power to the memory,
the tag being operable to read the memory and transmit data stored in the memory in response to the signal from the reader,
wherein the data is stored in the memory in a plurality of data units, each data unit having an associated sequence number,
the memory tag being operable to store the sequence number of the data unit to be transmitted in a register in the non-volatile memory, and
when power is supplied to the memory, the memory tag is operable to;
read a register stored in a non-volatile memory of the memory tag which stores a sequence number,
decrement the stored sequence number, read the data unit associated with the stored sequence number, transmit the data unit and increment the stored sequence number.
12. A memory tag according to claim 11 operable to repeat the steps of;
reading the register to read the stored sequence number,
reading the data unit associated with the stored sequence number and transmitting the data unit, and
incrementing the sequence number stored in the register.