1. A method of manufacturing a railroad freight car brake beam strut assembly, comprising the steps of:
providing a railroad freight car brake beam strut having an axially elongated slot defined between first and second sides of said strut, with each side of said strut defining a bore opening to a center and to an exterior of said strut, with the bores defined by said strut being aligned relative to each other along an axis; and
pressing a brake pin bushing into each bore of said strut in a direction extending away from the longitudinal axis of said strut, with each brake pin bushing first and second ends, and wherein a periphery of each bushing has a frusto-conical configuration disposed between said ends, with one end of the frusta-conical outer surface configuration on each bushing having a diameter smaller than an inner diameter defined by a closed margin of the respective bore in said strut, and with a second end of the frusta-conical outer surface configuration on each bushing having an outer diameter larger than the inner diameter defined by the closed margin of the respective bore in said strut.
2. A method of manufacturing a railroad freight car brake beam strut assembly, comprising the steps of
providing a railroad freight car brake beam strut having an axially elongated slot defined between first and second sides of said strut, with said first side of said strut defining a first bore opening to a center and to an exterior of said strut, and with the second side of said strut defining a second bore opening to said center portion and to the exterior of said strut, with said first and second bores defined by said strut being aligned relative to each other along an axis extending generally normal to a longitudinal axis of said strut;
pressing a first brake pin bushing into the first bore of said strut in a direction extending away from the longitudinal axis of said strut, with said first brake pin bushing having first and second ends, a bore opening to said first and second ends, and with a periphery of said first brake pin bushing having a frusta-conical surface configuration between said ends, with one end of the frusta-conical surface configuration on said first brake pin bushing having a diameter smaller than an inner diameter defined by a closed margin of the respective bore in said strut, and with a second end of the frusto-conical surface configuration on said first brake pin bushing having an outer diameter larger than the inner diameter defined by the closed margin of the respective bore in said strut; and
pressing a second brake pin bushing into the second bore of said strut in a direction opposed to the direction said first brake pin bushing is pressed into said first bore and extending away from the longitudinal axis of said strut, with said second brake pin bushing having first and second ends, a bore opening to said first and second ends, and a periphery of said second brake pin bushing having a frusta-conical surface configuration between said ends, with one end of the frusta-conical surface configuration on said second brake pin bushing having a diameter smaller than an inner diameter defined by a closed margin of the respective bore in said strut, and with a second end of the frusto-conical surface configuration on said second brake pin bushing having an outer diameter larger than the inner diameter defined by the closed margin of the respective bore in said strut.
3. The method of manufacturing a railroad freight car brake beam strut assembly according to claim 2 comprising the further step of:
repositioning said strut after said first brake pin bushing is pressed into said first bore and before said second brake pin bushing is pressed into said second bore in said strut.
4. The method of manufacturing a railroad freight car brake beam strut assembly according to claim 3 comprising the further step of:
inserting a tool operably coupled to a press through the opening in said first brake pin bushing and into engagement with the second brake pin bushing so as to press the second brake pin bushing into the second bore of said strut in a direction opposed to the direction said first brake pin bushing is pressed into said first bore and extending away from the longitudinal axis of said strut.
5. A railroad freight car brake beam strut assembly, comprising:
an elongated strut defining a longitudinal axis and an axially elongated slot between first and second joined walls of said strut, with the slot in said strut being inclined a predetermined number of degrees from vertical for accommodating an elongated brake lever extending through said strut, with each side wall of said strut defining a bore opening to a center and to an exterior of said strut, with the bores defined by the walls on said strut being aligned relative to each other to accommodate a brake lever pivot pin extending through strut thereby connecting the brake lever to said strut and so as to define an axis about which said brake lever pivots;
a pair of brake pin bushings, with one brake pin bushing being accommodated in each bore defined by the strut so as to journal said brake lever pivot pin, with each brake pin bushing first and second ends, and wherein a periphery of each bushing has a frusto-conical surface configuration disposed between said ends, with one end of the frusta-conical surface configuration on each bushing having a diameter smaller than an inner diameter defined by a closed margin of the respective bore in said strut, and with a second end of the frusto-conical surface configuration on each bushing having an outer diameter larger than the inner diameter defined by the closed margin of the respective bore in said strut.
6. The railroad freight car brake beam strut assembly according to claim 5, wherein each brake pin bushing is formed from powdered sintered metal material.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
That which is claimed is:
1. A digital N-finger rake receiver for a CDMA system, comprising
input means (MF) for receiving a digital scrambled and spreaded signal (DSN) constituted of chips having a duration Tc, oversampled with an oversampling factor Ns, and including delayed versions of at least one initial signal scrambled with at least one scrambling code, spreaded with at least one orthogonal code and transmitted by at least one emitter (BS1) on a multipath transmission channel a predetermined maximum delay spread Ds,
estimation means (SH) connected to the input means for estimating the number of paths of the channel, and their different time delay values, and
processing means for time aligning and descrambling, despreading, combining said delayed versions and delivering the data stream contained in the initial signal, characterized by the fact that the processing means comprise a time aligning and descrambling unit (DSU) including
a first delay chain (DCH1) connected to the input means and having N1 first outputs, N1 being equal to at least Ns1, the delay value between two adjacent first outputs being equal to TcNs,
a phase controllable scrambling code generator (SGA) for generating the scrambling code of the initial signal,
a second delay chain (DCH2A) connected to the output of the scrambling code generator and having 1DsTc second outputs, the delay value between two adjacent second outputs being equal to Tc,
first controllable selection means (MUX1) for selecting, for each path, one of the first outputs in response to a first control signal (CTR1),
second controllable selection means (MUX2) for selecting, for each path, one of the second outputs in response to a second control signal (CTR2),
an output module including main multiplication means (MTM) for multiplying, for each path, the elementary signal present at the selected first output with the elementary signal present at the selected second output, and
control means (CM) for delivering said first and second control signals for each path according to the time delay value of said considered path.
2. Receiver according to claim 1, characterized by the fact that N1 is equal to 2Ns1.
3. Receiver according to claim 2, characterized by the fact that said control means (CM) determine the difference between the greatest time delay value and the smallest time delay value among all the time delay values of the actual paths, by the fact that the path associated with the smallest time delay value is considered as a reference path, by the fact that said control means (CM) are adapted to select for this reference path, one specific first output of the first chain and one specific second output of the second chain, depending on said difference, and by the fact that the other selected first and second outputs associated to the other actual paths are determined in relation to said first and second specific outputs.
4. Receiver according to any one of the preceeding claims, characterized by the fact that the first delay chain is a chain composed of N11 first delay elements (DE1), each of which having an elementary delay value of TcNs, clocked by a first clock signal( CLK1) having a period of TcNs,
and by the fact that the second delay chain is a chain composed of DsTc second delay elements (DE2A), each of which having an elementary delay value of Tc, clocked by a second clock signal (CLK2) having a period of Tc.
5. Receiver according to any one of the preceeding claims, characterized by the fact that said control means are adapted to respectively successively deliver the first and second control signals (CTR1, CTR2) associated to the corresponding paths at a frequency of NTc,
by the fact that the first controllable selection means comprises a first register (RG1) connected to said first outputs of the first delay chain and clocked with a first register clock signal (CLK10) having a period of Tc, and a first multiplexer (MUX1) connected between the first register and one input of the main multiplication means (MTM), and successively controlled by said first control signals (CTR1),
by the fact that the second controllable selection means comprises a second register (RG2) connected to said second outputs and clocked with a second register clock signal (CLK20) having a period of Tc, and a second multiplexer (MUX2) connected between the second register and another input of the main multiplication means (MTM), and successively controlled by said second control signals (CTR2),
by the fact that the main multiplication means (MTM) comprises a single multiplier,
and by the fact that the output module further comprises a demultiplexer (DMUX1) connected to the output of the main multiplication means (MTM), having N outputs and controlled by a demultiplexer control signal (DCTR) at a frequency of NTc.
6. Receiver according to any one of the claims 1 to 4, characterized by the fact that said control means are adapted to respectively successively deliver the first and second control signals (CTR1, CTR2) associated to the corresponding actual paths at a frequency of NMTc,
by the fact that the first controllable selection means comprises a first register (RG1) connected to said first outputs and clocked with a first register clock signal having a period of Tc, and a first multiplexer (MUX1) connected between the first register and one input of the main multiplication means, and successively controlled by said first control signals,
by the fact that the second controllable selection means comprises a second register (RG2) connected to said second outputs and clocked with a second register clock signal having a period of Tc, and a second multiplexer (MUX2) connected between the second register and another input of the main multiplication means, and successively controlled by said second control signals,
by the fact that the main multiplication means comprises N parallel multipliers (MTM1, MTMN),
and by the fact that the output module further comprises a demultiplexer (DMUX1) connected to the output of the main multiplication means, having N outputs and controlled by a demultiplexer control signal at a frequency of NMTc.
7. Receiver according to any one of the preceeding claims, characterized by the fact that the time aligning and descrambling unit (DSU) comprises different scrambling code generators and different second delay chains respectively receiving different scrambling codes, each second delay chain having 1DsTc second outputs and a delay value between two adjacent second outputs equal to Tc.
8. Receiver according to any one of the preceeding claims, characterized by the fact that the estimation means (CHES) are further adapted to estimate the impulse response of each actual path, by the fact that the processing means further comprise a despreading and combining unit (DPRCU) connected to the output module of the time aligning and descrambling unit (DSU) and to the estimation means, (CHES) and by the fact that said despreading and combining unit comprises a storage means (MM) for storing said orthogonal code (OVSF), and supplementary multiplication means (SMTM) connected to the main multiplication means (MTM) and adapted for multiplying the signals delivered by the output module of the time aligning and descrambling unit, with said orthogonal code (OVSF).
9. Digital information receiving device, in particular a cellular mobile phone, characterized by the fact it incorporates a rake receiver as defined in any one of the preceeding claims.