1. A pharmaceutical composition comprising a chimeric or humanized antibody that specifically binds to an epitope within residues 3-7 of A and a pharmaceutical carrier.
2. The pharmaceutical composition of claim 2, which is a sustained release compositions
3. The pharmaceutical composition of claim 2, wherein the carrier is a physiologically acceptable diluent for parenteral administration.
4. A pharmaceutical composition comprising a chimeric or humanized antibody that specifically binds to an epitope within residues 3-7 of A and a pharmaceutical carrier, wherein the isotype of the antibody is human IgG1, which is a sustained release composition.
5. (Canceled)
7. A pharmaceutical composition comprising a chimeric or humanized antibody that specifically binds to an epitope within residues 3-7 of A and a pharmaceutical carrier, wherein the isotype of the antibody is human IgG1, wherein the carrier is a physiologically acceptable diluent for parenteral administration.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A low-noise amplifier comprising:
an input transconductance stage that receives an input voltage signal;
a cascode transistor pair that is coupled to the input transconductance stage to generate an amplified output signal; and
an output load stage coupled to the amplified output signal, wherein the output load stage comprises a first load resistor coupled to an adjustable current source branch in parallel.
2. The low-noise amplifier of claim 1, wherein the output load stage further comprises a switchable branch coupled to the first load resistor and the adjustable current source branch in parallel, wherein the switchable branch comprises a second load resistor connected to a load switch in serial to select a gain mode.
3. The low-noise amplifier of claim 1, wherein the adjustable current source branch comprises a current mirror load transistor pair.
4. The low-noise amplifier of claim 3, wherein the adjustable current source branch further comprises a first degeneration resistor connected to the current mirror load transistor in serial.
5. The low-noise amplifier of claim 3, wherein the output load stage further comprises a control transistor to supply a control signal to a gate of the current mirror load transistor pair to adjust a first current sourced by the current mirror load transistor pair, wherein source current of the control transistor is controlled by a control current.
6. The low-noise amplifier of claim 5, wherein the control transistor is connected to a second degeneration resistor in serial.
7. The low-noise amplifier of claim 1, further comprising a current source to supply current to the input transconductance stage.
8. A method for gain adjustable low-noise amplifier, the method comprising:
providing an input transconductance stage to receive an input voltage signal;
coupling a cascode transistor pair to the input transconductance stage to generate an amplified output signal;
coupling a first load resistor to the amplified output signal;
coupling an adjustable current source branch to the first load resistor in parallel; and
adjusting DC operation point of the amplified output signal according to a change of equivalent resistance associated with the load resistor and the adjustable current source branch to obtain a desired gain of the low-noise amplifier, wherein the adjustable current source branch comprises a current mirror load transistor pair having a gate coupled to a control signal for adjusting first current of the current mirror load transistor pair.
9. The method of claim 8, further comprising:
providing a switchable impedance branch coupled to the first load resistor in parallel to select a gain mode.
10. The method of claim 8, further comprising:
providing a first degeneration resistor coupled to the current mirror load transistor to reduce noise associated with the current mirror load transistor pair and increase output resistance of the current mirror load transistor pair.
11. The method of claim 8, further comprising:
providing a control transistor to generate the control signal coupled to the gate adjusting first current sourced by the current mirror load transistor pair.
12. The method of claim 11, further comprising:
providing a control current to the control transistor to generate the control signal.