1. A spiral inductor comprising:
a substrate;
an inductor dielectric layer over the substrate having a spiral opening provided therein; and
a spiral inductor in the spiral opening, the spiral inductor including;
a plurality of parallel spiral vias connected together at center proximate and center distal ends of the spiral inductor and only along a top or bottom edge.
2. The spiral inductor as claimed in claim 1 wherein:
the spiral inductor includes:
a spiral line in the spiral opening; and
the plurality of parallel spiral vias above the spiral line and integral therewith.
3. The spiral inductor as claimed in claim 1 wherein:
the spiral inductor includes:
a spiral line over the plurality of parallel spiral vias and integral therewith.
4. The spiral inductor as claimed in claim 1 including:
a first connecting portion;
connecting via between the first connecting portion and the center proximate end of the spiral inductor; and
a second connecting portion connected to the center distal end of the spiral inductor.
5. The spiral inductor as claimed in claim 1 wherein:
the spiral opening forms a multi-turn spiral from a group consisting of square, rectangular, and circular spirals.
6. A spiral inductor comprising:
a substrate;
a field dielectric layer over the substrate;
an inductor dielectric layer over the field dielectric layer having a spiral opening provided therein;
a spiral inductor in the spiral opening, the spiral inductor including:
a plurality of parallel spiral vias connected together at center proximate and center distal ends of the spiral inductor and only along a top or bottom edge;
a first connecting portion connected to the center proximate end of the spiral inductor; and
a second connecting portion connected to the center distal end of the spiral inductor.
7. The spiral inductor as claimed in claim 6 wherein:
the spiral inductor includes:
a spiral line in the spiral opening connected together to the parallel spiral vias at the center proximate and the center distal ends of the spiral inductor; and
the plurality of parallel spiral vias above the spiral line and integral therewith.
8. The spiral inductor as claimed in claim 6 wherein:
the spiral inductor includes:
a spiral line over the plurality of parallel spiral vias and integral therewith, the spiral line connected together to the parallel spiral vias at the center proximate and the center distal ends of the spiral inductor.
9. The spiral inductor as claimed in claim 6 including:
a connecting portion dielectric layer over the field dielectric and under the inductor dielectric layer, the connecting portion dielectric layer having an opening provided therein for the first connecting portion;
connecting via between the first connecting portion and the center proximate end of the spiral inductor; and
a second connecting portion connected to the center distal end of the spiral inductor.
10. The spiral inductor as claimed in claim 6 wherein:
the spiral opening forms a multi-turn spiral from a group consisting of square, rectangular, and circular spirals.
11. The spiral inductor as claimed in claim 6 wherein:
the spiral inductor is fabricated by an aluminum vialine process or a copper damascene process.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
forming a first transistor above a first device region, said first transistor comprising a first gate electrode structure and first sourcedrain regions;
forming a second transistor above a second device region, said second transistor comprising a second gate electrode structure and second sourcedrain regions;
forming an etch stop layer at least above each of said first and second gate electrode structures and each of said first and second sourcedrain regions of said first and second transistors;
forming a sacrificial layer above said etch stop layer;
exposing gate electrode material of each of said first and second gate electrode structures after forming said etch stop and sacrificial layers;
replacing said first gate electrode structure with a first replacement gate structure comprising a high-k dielectric material and a first metal-containing gate electrode material while covering said second transistor by a mask;
removing said second gate electrode structure on the basis of a first selective etch process while said first replacement gate electrode structure is also exposed to said selective etch process;
forming a second replacement gate electrode structure comprising a high-k material and a second metal-containing gate electrode material;
after forming said second replacement gate electrode structure, performing a second selective etch process on the basis of said etch stop layer to remove said sacrificial layer from above at least one of said first and second transistors; and
after removing said sacrificial layer, removing said etch stop layer from above said at least one of said first and second transistors.
2. The method of claim 1, wherein said first selective etch process is performed on the basis of an etch chemistry comprising tetramethyl ammonium hydroxide (TMAH).
3. The method of claim 1, further comprising selectively removing material of said first and second replacement gate electrode structures to form recesses therein and refilling said recesses with a third metal-containing material.
4. The method of claim 1, wherein said first metal-containing material has a first work function and said second metal-containing material has a second work function differing from said first work function.
5. The method of claim 1, further comprising forming a dielectric layer having an intrinsic stress above at least one of said first and second transistors after removing said sacrificial layer.
6. The method of claim 1, further comprising, while removing said etch stop layer, removing at least a portion of a sidewall spacer structure formed on sidewalls of at least one of said first and second transistors.
7. The method of claim 1, further comprising forming a third transistor having a third gate electrode structure above a third device region and maintaining at least a portion of gate electrode material of said third gate electrode structure when replacing said first gate electrode structure and removing said second gate electrode structure.
8. The method of claim 7, wherein forming said first, second and third transistors comprises forming a gate insulation layer for said first, second and third transistors so as to have characteristics required for forming said third transistor.
9. The method of claim 1, wherein exposing gate electrode material of each of said first and second gate electrode structures comprises removing excess material of said sacrificial layer by performing a first chemical-mechanical polishing process based on said etch stop layer.
10. The method of claim 9, further comprising performing a second chemical-mechanical polishing process to remove at least a portion of each of said sacrificial and etch stop layers, and an upper portion only of each of said first and second gate electrode structures.
11. The method of claim 1, wherein exposing gate electrode material of each of said first and second gate electrode structures comprises removing only an upper portion of each of said first and second gate electrode structures using said sacrificial layer prior to replacing said first gate electrode structure.
12. The method of claim 11, wherein replacing said first gate electrode structure comprises selectively etching gate electrode material of said first gate electrode structure after removal of said upper portion thereof to expose a dielectric gate insulation material, removing said dielectric gate insulation material, and forming a dielectric replacement gate insulation material comprising said high-k material.
13. The method of claim 12, wherein forming said dielectric replacement gate insulation material comprises forming a first dielectric material and forming said high-k dielectric material on said first dielectric material.
14. The method of claim 12, wherein gate electrode material of said first gate electrode structure is removed by a selective dry etch process.
15. The method of claim 12, wherein gate electrode material of said first gate electrode structure is removed by a selective wet etch process.
16. A method, comprising:
forming a first gate electrode structure in a first device region and a second gate electrode structure in a second device region, each of said first and second gate electrode structures comprising a gate insulation dielectric and a gate electrode material, said gate insulation dielectric having a first thickness according to a design thickness of said second gate electrode structure;
forming an etch stop layer and a sacrificial layer above each of said first and second gate electrode structures and above sourcedrain regions of each of said first and second gate electrode structures;
removing an upper portion of said first and second gate electrode structures to expose said gate electrode material based on said etch stop and sacrificial layers;
forming a mask to cover said second gate electrode structure;
selectively removing said gate electrode material and said gate insulation layer of said first gate electrode structure;
replacing said first gate electrode structure by a first replacement gate electrode structure comprising a first high-k dielectric material and a first conductive metal-containing material while maintaining said gate insulation dielectric and a portion of said gate electrode material of said second gate electrode structure; and
after replacing said first gate electrode structure, removing said sacrificial layer and said etch stop layer from above said sourcedrain regions of at least one of said first and second gate electrode structures.
17. The method of claim 16, further comprising forming a conductive material on said first replacement gate electrode structure and said second gate electrode structure in a common process sequence.
18. The method of claim 16, wherein replacing said first gate electrode structure further comprises forming a dielectric material after removal of said gate insulation layer and depositing said first high-k dielectric material on said dielectric material.
19. The method of claim 16, further comprising forming a third gate electrode structure of a third transistor above said first device region, and replacing said third gate electrode structure with a second replacement gate electrode structure including a second high-k material and a second conductive metal-containing gate electrode material.
20. The method of claim 19, further comprising forming a first stress-inducing layer above said first transistor and a second stress-inducing layer above said third transistor, said first and second stress-inducing layers having a different type of intrinsic stress.
21. The method of claim 19, wherein replacing said third gate electrode structure comprises removing said third gate electrode structure on the basis of a selective etch process without covering said first replacement gate electrode structure and said second gate electrode structure.
22. The method of claim 21, wherein said selective etch process is performed on the basis of TMAH.