1. A register circuit adapted to store data, the register circuit comprising:
a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input; and
a control circuit coupled to the master-slave flip flop, the control circuit receiving a reference clock signal and generating the slave clock signal which is delayed relative to a master clock signal;
wherein the control circuit comprises a first delay element establishing a pulse width of the slave clock signal, and a second delay element establishing a delay of the slave clock signal relative to the master clock signal.
2. The register circuit of claim 1, wherein the slave clock signal is delayed relative to the master clock signal by reducing the width of the pulse of the slave clock signal.
3. The register circuit of claim 1, wherein the first delay element is coupled to receive the reference clock signal and generate the slave clock signal.
4. The register circuit of claim 3, wherein the second delay element is coupled to receive the reference clock signal and generate the master clock signal.
5. The register circuit of claim 1, further comprising a slave pulse generator coupled to receive a delayed reference clock signal, wherein the slave clock signal generated by the slave pulse generator comprises a pulse.
6. The register circuit of claim 5, wherein the pulse generated by slave pulse generator is in a first half of a clock cycle of the reference clock signal.
7. The register circuit of claim 1, further comprising a slave pulse detector coupled to receive the master clock signal and the slave clock signal, the slave pulse detector controlling the generation of a pulse of the master clock signal.
8. A register circuit adapted to store data, the register circuit comprising:
a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input, a master clock signal and a slave clock signal;
a slave pulse generator coupled to the master-slave flip flop, the slave pulse generator receiving a reference clock signal and generating the slave clock signal which is delayed relative to the master clock signal; and
a slave pulse detector coupled to receive the master clock signal and the slave clock signal, the slave pulse detector controlling the generation of the master clock signal.
9. The register circuit of claim 8, wherein the slave pulse generator comprises a first delay element which reduces the pulse width of the slave clock circuit.
10. The register circuit of claim 9, wherein the slave pulse detector comprises a second delay element adapted to delay an edge of the master clock signal relative to the slave clock signal.
11. The register circuit of claim 8, wherein the slave pulse detector comprises a set-reset flip flop coupled to receive the master clock signal at a set input and the slave clock signal at a reset input.
12. The register circuit of claim 11, wherein the slave pulse detector further comprises a NAND gate coupled to an output of the set-reset flip flop and an output of the slave pulse generator.
13. The register circuit of claim 8, wherein a slave clock pulse is generated after a delay which is greater than one half of a clock cycle.
14. The register circuit of claim 8, further comprising a rising clock edge detector coupled to receive the reference clock signal and an output of the slave pulse detector.
15. A method of storing data in a register circuit, the method comprising:
coupling data to a master-slave flip flop;
coupling a reference clock signal to a control circuit;
generating a slave clock signal using a first delay element to establish a pulse width of the slave clock signal;
establishing a delay of the slave clock signal relative to a master clock signal using a second delay element; and
coupling the master clock signal and the slave clock signal to the master-slave flip flop.
16. The method of claim 15, wherein delaying the slave clock signal relative to the master clock signal comprises shortening the pulse width of the slave clock signal.
17. The method of claim 15, wherein generating a slave clock signal comprises generating the slave clock signal within one half of the clock cycle of the reference clock signal.
18. The method of claim 15, further comprising receiving the reference clock signal at a delay element and generating the master clock signal at the output of the delay element.
19. The method of claim 15, further comprising coupling a slave pulse generator to the second delay element, the slave pulse generator having the first delay element for shaping a slave pulse of the slave clock signal.
20. The device of claim 15, further comprising coupling the master clock signal and the slave clock signal to a slave pulse detector, the slave pulse detector delaying the generation of an edge of the master clock signal relative to the slave clock signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure, the method comprising the steps of:
forming a mask layer overlying the electrically conductive electrode;
patterning said mask layer to form an exposed electrically conductive electrode material;
removing at least a portion of said exposed electrically conductive electrode material while forming an electrically conductive veil adjacent said mask layer; and
forming a metal contact layer such that said metal contact layer contacts said electrically conductive veil.
2. The method of claim 1, wherein the step of forming a mask layer comprises forming a hardmask formed of one of silicon dioxide and silicon nitride.
3. The method of claim 1, wherein the step of forming a mask layer comprises forming a photoresist layer.
4. The method of claim 1, further comprising the steps of forming and developing a photoresist layer overlying said mask layer before the step of patterning.
5. The method of claim 1, wherein the step of removing at least a portion of said exposed electrically conductive electrode comprises removing by one of ion milling, inert gas sputter etching and reactive ion etching.
6. The method of claim 1, wherein, before the step of forming a metal contact layer, the method further comprises the steps of:
forming a second dielectric material layer overlying said electrically conductive veil and a remaining exposed portion of said structure; and
removing a portion of said second dielectric material layer to expose an area of said electrically conductive veil sufficient for electrical contact.
7. A method for contacting an electrode for a magnetoelectronics element that is electrically connected to the electrode, the magnetoelectronics element having a first magnetic layer overlying a tunnel barrier layer that overlies a second magnetic layer, the method comprising the steps of:
forming a mask layer overlying the electrode;
patterning said mask layer to form an exposed electrode material;
removing at least a portion of said exposed electrode material while forming an electrically conductive veil adjacent said mask layer;
forming a dielectric material layer overlying said electrically conductive veil; and
removing a portion of said dielectric material layer to expose an area of said electrically conductive veil sufficient for electrical contact.
8. The method of claim 7, further comprising the step of forming a metal contact layer overlying said dielectric material layer, said metal contact layer contacting said electrically conductive veil.
9. The method of claim 7, wherein the step of removing at least a portion of said exposed electrode material forms an exposed first magnetic layer material and further comprising the step of removing at least a portion of said exposed first magnetic layer material.
10. The method of claim 9, wherein the step of removing at least a portion of said exposed first magnetic layer material forms a residual exposed first magnetic layer material and further comprising the step of oxidizing said residual exposed first magnetic layer material before the step of forming a dielectric material layer.
11. The method of claim 7, wherein the step of forming a mask layer comprises forming a hardmask of one of silicon dioxide and silicon nitride.
12. The method of claim 7, wherein the step of forming a mask layer comprises forming a photoresist layer.
13. The method of claim 12, further comprising the step of removing said mask layer before the step of forming a dielectric material layer.
14. The method of claim 7, further comprising the steps of forming and developing a photoresist layer overlying said mask layer before the step of patterning.
15. The method of claim 9, wherein the step of removing at least a portion of said exposed first magnetic layer comprises forming an electrically conductive veil that comprises material from both the electrode and the first magnetic layer.
16. The method of claim 7, wherein the step of removing at least a portion of said exposed electrode material comprises removing by one of ion milling, inert gas sputter etching and reactive ion etching.
17. A random access memory device having a metal contact layer and a plurality of magnetic memory units electrically coupled to the metal contact layer, each magnetic memory unit comprising:
a magnetoelectronics element;
an electrode overlying said magnetoelectronics elements; and
an electrically conductive veil, wherein said electrically conductive veil electrically couples said electrode and said metal contact layer.
18. The random access memory device of claim 17, said electrically conductive veil comprised of a material of which said electrode is comprised.
19. The random access memory device of claim 17, said magnetoelectronics element having a magnetic layer, wherein said electrically conductive veil is comprised of materials that comprise said electrode and said magnetic layer.
20. The random access memory device of claim 17, said magnetoelectronics element comprising one of a magnetic tunnel junction element and a giant magneto resistance element.