1. A system comprising:
an interconnect bus having a plurality of signal traces;
a first integrated circuit having:
a transmitter controller, and
a transmitter interface circuit coupled to the transmitter controller to receive first data synchronously with a system clock signal, to generate a bus clock signal, to convert the first data into second data synchronous with transitions of the bus clock signal and to output the second data to the interconnect bus; and
a second integrated circuit having:
a receiver controller configured to generate at least one control signal indicative of a bit-lane correspondence between the first integrated circuit and the second integrated circuit, and
a receiver interface circuit coupled to the interconnect bus to retrieve the second data and coupled to the receiver controller to receive the at least one control signal, wherein the receiver interface circuit restores the first data according to the at least one control signal.
2. The system of claim 1, wherein the transmitter controller generates predetermined test data and provides a pseudo-random sequence to the transmitter interface circuit for transmission to the second integrated circuit.
3. The system of claim 2, wherein the receiver controller generates like predetermined test data, compares the like predetermined test data to data received by the receiver interface circuit, and determines a transmission error rate of the interconnect bus.
4. The system of claim 1, wherein the receiver controller comprises a circuit to deduce a bit-lane correspondence between the outputs of the transmitter interface circuit and inputs of the receiver interface circuit.
5. The system of claim 4, wherein the receiver controller comprises a circuit to deduce a phase offset between a rising transition of the bus clock signal and a rising transition of the system clock signal.
6. The system of claim 5, wherein the receiver controller generates the control signal according to the bit-lane correspondence and the phase offset.
7. The system of claim 1, wherein the receiver controller compares at least one portion of the second data to a plurality of predetermined patterns each corresponding to one of a plurality of bit-lane correspondences.
8. The system of claim 1, wherein the receiver controller compares at least one portion of the second data to at least two predetermined patterns corresponding to at least two phase offsets between a rising transition of the bus clock signal and a rising transition of the system clock signal.
9. A system comprising:
an interconnect bus having a plurality of signal traces;
a first integrated circuit having:
a transmitter controller,
a transmitter interface circuit coupled to the transmitter controller to receive first data synchronously with a system clock signal, to generate a bus clock signal, to convert the first data into second data synchronous with transitions of the bus clock signal and to output the second data to the interconnect bus; and
a second integrated circuit having:
a receiver controller configured to generate control signals indicative of a phase offset between a rising transition of the bus clock signal and a rising transition of the system clock signal from the second data, and
a receiver interface circuit coupled to the interconnect bus to retrieve the second data and configured to restore the first data according to the control signals.
10. The system of claim 9, wherein the transmitter controller generates predetermined test data and provides a pseudo-random sequence to the transmitter interface circuit for transmission to the second integrated circuit.
11. The system of claim 10, wherein the receiver controller generates like predetermined test data, compares the like predetermined test data to data received by the receiver interface circuit, and determines a transmission error rate of the interconnect bus.
12. The system of claim 9, wherein the receiver controller comprises a circuit to deduce a bit-lane correspondence between the outputs of the transmitter interface circuit and the inputs of the receiver interface circuit.
13. The system of claim 12, wherein the receiver controller generates the control signals consistent with the bit-lane correspondence and the phase offset.
14. The system of claim 9, wherein the receiver controller compares at least one portion of the second data to a plurality of predetermined patterns each corresponding to one of a plurality of bit-lane correspondences.
15. The system of claim 9, wherein the receiver controller compares at least one portion of the second data to at least two predetermined patterns corresponding to at least two phase offsets between a rising transition of the bus clock signal and a rising transition of the system clock signal.
16. A method for communicating data from a first integrated circuit to a second integrated circuit across an interconnect bus within a system, the method comprising:
upon receiving a reset signal, the first integrated circuit and the second integrated circuit performing a set up process that comprises deducing a bit-lane correspondence of the interconnect bus;
transmitting data from the first integrated circuit to the second integrated across the interconnect bus; and
reconstructing the data at the second integrated circuit according to the deduced bit-lane correspondence.
17. The method of claim 16, wherein the deducing step comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit; and
at the second integrated circuit, comparing at least a portion of received data to a plurality of predetermined patterns each corresponding to one of a plurality of bit-lane correspondences of the interconnect bus.
18. The method of claim 16, wherein the setup process comprises deducing a phase offset between a rising transition of a clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
19. The method of claim 16, wherein the set up process comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit;
at the second integrated circuit, comparing at least a portion of received data to at least two predetermined patterns each corresponding to one of at least two phase offsets between a rising transition of the clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
20. The method of claim 16, wherein the set up process comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit;
at the second integrated circuit, generating like predetermined test data and comparing data received by the second integrated circuit to the like predetermined test data to determine a transmission error rate of the interconnect bus.
21. A method for communicating data from a first integrated circuit to a second integrated circuit across an interconnect bus within a system, the method comprising:
upon receiving a reset signal, the first integrated circuit and the second integrated circuit performing a set up process that comprises deducing a phase offset between a rising transition of a clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit;
transmitting data from the first integrated circuit to the second integrated across the interconnect bus; and
reconstructing the data at the second integrated circuit according to the deduced phase offset.
22. The method of claim 21, wherein the deducing step comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit;
at the second integrated circuit, comparing at least a portion of received data to at least two predetermined patterns each corresponding to one of at least two phase offsets between a rising transition of the clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
23. The method of claim 21, wherein the set up process comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit;
at the second integrated circuit, generating like predetermined test data and comparing data received by the second integrated circuit to the like predetermined test data to determine a transmission error rate of the interconnect bus.
24. An integrated circuit, comprising:
means for coupling to another integrated circuit via an interconnect bus;
means for deducing a bit-lane correspondence of the interconnect bus;
means for receiving data from the other integrated circuit via the interconnect bus; and
means for reconstructing data transmitted by the other integrated circuit according to the deduced bit-lane correspondence.
25. The integrated circuit of claim 24, wherein the means for deducing comprises:
means for comparing at least a portion of the received data to a plurality of predetermined patterns each corresponding to one of a plurality of bit-lane correspondences of the interconnect bus.
26. The integrated circuit of claim 24, comprising
second means for deducing a phase offset between a rising transition of a clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
27. The integrated circuit of claim 26, wherein the second means for deducing comprises:
means for comparing at least a portion of the received data to at least two predetermined patterns each corresponding to one of at least two phase offsets between a rising transition of the clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
28. The integrated circuit of claim 24, comprising:
means for generating predetermined test data; and
means for comparing the received data to the predetermined test data to determine a transmission error rate of the interconnect bus.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A non-transitory computer readable medium, comprising:
a computer program code including executable instructions, which, when executed by a terminal device, cause the terminal device to perform a method for cell reselection as follows:
receiving, when in a cell of a Long Term Evolution (LTE) system, a message including a dedicated priority list from the LTE system; and
performing, when camping on a cell of a non-LTE system, the cell reselection in accordance with the received dedicated priority list before a valid time of the dedicated priority list expires.
2. The non-transitory computer readable medium of claim 1, wherein the message received from the LTE system includes a dedicated signaling, the dedicated priority list being included in the dedicated signaling.
3. The non-transitory computer readable medium of claim 1, wherein the dedicated signaling including the dedicated priority list includes a Radio Resource Control (RRC) Connection Release message.
4. The non-transitory computer readable medium of claim 1, wherein the method further comprises: performing, when camping on the cell of the non-LTE system, the cell reselection in accordance with a public priority list after the valid time of the dedicated priority list expires.
5. The non-transitory computer readable medium of claim 4, wherein the public priority list is obtained from the LTE system or the non-LTE system.
6. The non-transitory computer readable medium of claim 5, wherein the public priority list is obtained through system broadcast information.
7. The non-transitory computer readable medium of claim 1, wherein the method further comprises: deleting the dedicated priority list when the valid time of the dedicated priority list expires.
8. The non-transitory computer readable medium of claim 1, wherein the valid time of the dedicated priority list is controlled through a timer.
9. The non-transitory computer readable medium of claim 1, wherein the valid time of the dedicated priority list is obtained through a dedicated signaling from the LTE system.
10. The non-transitory computer readable medium of claim 9, wherein the dedicated signaling includes a Radio Resource Control (RRC) Connection Release message, the valid time being included in the RRC Connection Release message.
11. The non-transitory computer readable medium of claim 1, wherein the valid time is included in a dedicated signaling.
12. The non-transitory computer readable medium of claim 1, wherein the dedicated priority list comprises priority information of different frequencies or priority information of different radio access technologies (RATs).
13. The non-transitory computer readable medium of claim 12, wherein the priority information comprises priority information of frequencies of the different RATs.
14. The non-transitory computer readable medium of claim 1, wherein the dedicated priority list comprises frequency priority information of the LTE system and the non-LTE system.
15. An apparatus comprising:
a non-transitory storage medium including executable instructions; and
a processor;
wherein the executable instructions, when executed by the processor, cause the apparatus to:
receive, when in a cell of a Long Term Evolution (LTE) system, a message including a dedicated priority list from the LTE system; and
perform, when camping on a cell of a non-LTE system, cell reselection in accordance with the received dedicated priority list before a valid time of the dedicated priority list expires.
16. The apparatus of claim 15, wherein the message received from the LTE system includes a dedicated signaling, the dedicated priority list being included in the dedicated signaling.
17. The apparatus of claim 15, wherein the dedicated signaling containing the dedicated priority list includes a Radio Resource Control (RRC) Connection Release message.
18. The apparatus of claim 15, wherein the valid time of the dedicated priority list is controlled through a timer.
19. The apparatus of claim 15, wherein, in a situation where the apparatus camps on the cell of the non-LTE system and after the valid time of the dedicated priority list expires, the executable instructions, when executed by the processor, cause the processor to perform the cell reselection in accordance with a public priority list obtained from the LTE network or the non-LTE network.
20. The apparatus of claim 15, wherein the dedicated priority list comprises priority information of different frequencies or of different radio access technologies (RATs).